Spin qubits are a promising candidate for large-scale fault-tolerant quantum computing due to <1µm2 footprint per qubit, higher operating temperature (up to 1K [1]) and possible compatibility with industrial CMOS processes [2], [3]. However, the need for a simultaneous ~µs readout of thousands of devices is especially challenging in terms of power consumption and footprint per qubit [4], [5]. Frequency-domain multiplexed (FDM) reflectometry architectures using cryo-CMOS have been introduced in [6], [7], [8] but these circuits require bulky > 100µm2 inductors and do not match readout time specifications using actual quantum devices. Besides, current integrator readout schemes have been proposed [9], [10], but offer no scaling perspectives beyond time-domain multiplexing, leading to strong constraints in terms of bandwidth and power consumption. Recently, [4] introduced a capacitive-feedback transimpedance amplifier achieving an inductor-less FDM readout of two quantum dots [11]. Nevertheless, the demonstrated power consumption per qubit of 214µW/qubit remains too high to match the maximum heat dissipation allowed near quantum devices [12] in a large-scale perspective. Moreover, the used On-Off Keying (OOK) modulations are limited to one qubit per carrier, thus requiring high bandwidth and power consumption in order to read thousands of qubits.

This paper proposes a comprehensive model of capacitive feedback transimpedance amplifiers, based on an analysis of the parasitics and non-idealities of the system. The proposed model is in good agreement with circuit simulations (less than 2% error on the gain and 18% on the bandwidth for large set of parameters), and allows to compute the analytical boundaries of the capacitive topology. Finally, a comparative assessment between capacitive and resistive topologies in terms of performance is proposed and highlights the salient performances of capacitive feedback transimpedance amplifiers.