The current Electronic Design Automation (EDA) tools focus on a component-level design perspective, based on modifying its physical dimensions and electrical parameters. Although this approach works, this forces a design space that often becomes unmanageable, leading to an excessive brute-force solution that results in an unnecessary overuse of resources. This thesis proposes an approach for the detection of fundamental subcircuit structures, also known as functional structures or primitives, contributing to the compartmentalization of the design space and thus to the Analog Design Automation Flow. The classification and detection of these structures is not trivial, and it has become a major challenge for future development. Some previous proposed approaches have demonstrated an overall good detection ratio, yet with non realistic limitations in such a diverse field as analog design, including its complexity in time or high number of primitive variations, among others. This thesis proposes a new approach for the identification of components functionality using Graph Neural Networks (GNN). The proposed scheme uses a node classification problem approach together with a compound graph, enabling the functionality detection of each transistor in the circuit. This detection is based on a sub-graph isomorphism subsystem, which annotates the information during the creation of the dataset. This differs from other previous approaches, such as graph classification or linking prediction, being one of the firsts in its kind. This system has reached an accuracy of > 97% in component classification, even with unbalanced data, being easily expansible, robust and scalable. Future work will focus on the incorporation of more complex data within the proposed flow using NXP data, and the study of a topology identification approach, so that 100% can be reached.