Nanopyramidal Texturing of c-Si Wafers for Silicon Heterojunction Bottom Cells in Perovskite–Silicon Tandems

Abstract

Perovskite–silicon tandem solar cells can exceed the single-junction silicon efficiency limit by combining a wide-bandgap perovskite top cell with a crystalline-silicon bottom cell, but the silicon bottom cell must absorb transmitted long-wavelength light efficiently while remaining compatible with the thin layers deposited above it. Since surface texturing reduces reflection and improves light trapping but conventional micrometre-scale pyramids can be too large for conformal perovskite deposition, this thesis investigates wet-chemical nanopyramidal texturing of double-side-textured c-Si wafers for silicon heterojunction (SHJ) bottom-cell test structures.

A standard KOH–MonoTEX H2.6 texturing process and a silicate-assisted KOH–K2SiO3–MonoTEX H2.6 nanotexturing process were developed and compared, with the resulting surface morphology quantified using an improved semi-automated Pyramid Height Estimation tool applied to top-view scanning electron microscopy images. The tool extracts pyramid-height distributions, including the mean height and the 95th-percentile height, h95, defined as the height below which 95% of the detected pyramids fall. These morphology metrics were combined with average reflectance measurements over 300–1200 nm. Selected textures were then processed into symmetric SHJ bottom-cell test structures with (i )/(n) and (i )/(p) Si-based thin-film stacks. These symmetric structures do not represent complete solar cells, but isolate whether each
texture can be passivated and contacted under the selected SHJ process flow. Their electrical quality was evaluated by measuring the effective minority-carrier lifetime after PECVD deposition of these stacks, after ITO sputtering and after annealing, followed by effective contact-resistivity extraction after metallisation.

The pre-texturing nitric acid oxidation cycle (NAOC) was essential for obtaining uniformwet-etched surfaces and reducing untextured regions. For standard KOH–MonoTEX texturing, increasing the bath temperature from 70 to 80 ◦C improved the average reflectance, whereas increasing theMonoTEX H2.6 volume from 30 to 50mL did not further improve the optical response. The selected standard texture, obtained after 8 min at 80 ◦C with 30 mLMonoTEX H2.6, achieved the lowest standard-texture average reflectance of 14.956% over
300–1200 nm and served as the optical benchmark. For silicate-assisted nanotexturing, K2SiO3 moderated pyramid growth and enabled sub-micrometre mean heights, with the 10 min process at 70 ◦C using 50 mL MonoTEX H2.6 and 55/110 g KOH/K2SiO3 providing the best balance between morphology and optics: side-averaged mean heights of 0.682 and 0.702 μm on the front and rear sides, h95 = 1.327 μm on both sides, and an average reflectance of 15.826%.

The electrical characterisation showed that the selected textures could be processed into SHJ bottom-cell test structures withmeasurable passivation and contact-resistivity performance. Valid n-type structures reached effective minority-carrier lifetimes above 20 ms after PECVD, while p-type structures showed lower recovered lifetimes of approximately 2–4 ms, consistent with the stronger process sensitivity of the investigated p-type contact stack. ITO sputtering caused a strong temporary lifetime loss, but annealing recovered a substantial part of the lost passivation quality. The extracted effective contact resistivities did not show a simple dependence on nanotexturing time or pyramid height, but were more strongly influenced by contact-stack and run-to-run variation, with valid n-type values mainly between 80 and 120mΩ·cm^2 and valid p-type values spanning approximately 64–141mΩ·cm^2.

Overall, the selected standard texture remains the lowest-reflectance benchmark, whereas the 10 min silicate-assisted nanotexture provides the best tandem-oriented compromise between reduced pyramid height, controlled upper-tail morphology, optical response, recovered passivation quality and effective contact resistivity. Further work should increase the sample size, validate SEM-based height estimates with direct three-dimensional measurements, and improve bath-conditioning and PECVD reproducibility.

Beyond the symmetric test structures studied here, controlled nanotextured c-Si surfaces have also been reported in approximately 31% perovskite–silicon tandem devices and, outside photovoltaics, as nanotextured Si/SiO2 templates for low-impedance multilayer graphene neural electrodes [1], [2].