Cryogenic Hot Carrier Degradation and Threshold-Voltage Turn-Around Effect in 5-V CMOS Transistors

Abstract

This paper presents the first cryogenic characterization of Hot Carrier Degradation (HCD) in 5-V thick-oxide transistors fabricated in a 160-nm CMOS technology. HCD significantly worsens in nMOS devices at 4.2 K, leading to a more severe degradation, especially of threshold voltage and current in the linear regime. Contrary to expectations, pMOS devices exhibit a temporary performance improvement after stress, showing for the first time at 4.2 K a HCD-induced turn-around effect in threshold voltage and current. The threshold-voltage shift follows a power law with stress time, showing a much higher exponent at $4.2 K$ than at $300 K$ for nMOS, but not for pMOS devices. The threshold-voltage shift also follows a power law with stress voltage, strongly accelerated for nMOS at 4.2 K, but unchanged for pMOS.