A 74fs-Jitter, −59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying Dual-Ramp DTC
Rishabh Gurbaxani (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Cicero S. Vaucher (NXP Semiconductors, TU Delft - Electrical Engineering, Mathematics and Computer Science)
Masoud Babaie (TU Delft - QCD/Babaie Lab, TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
This work presents a fractional-N digital PLL that employs a supply-resilient, time-amplifying dual-ramp DTC, which offers 8× time amplification and maintains its linearity under supply variations. Additionally, a DTC code-randomization technique is included to enhance the DTC gain-calibration accuracy and convergence speed at near-integer channels. The PLL achieves <-59dBc fractional spurs and 74fs rms jitter for a stable supply and 88.5fs rms jitter for a 29mVrms, 10MHz-bandwidth supply noise.
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