A 3V 15b 157W Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing

Conference Paper (2022)
Authors

L.A. Enthoven (QCD/Sebastiano Lab)

J. Van Staveren (QCD/Sebastiano Lab)

J. Gong

M Babaie (TU Delft - Electronics)

F. Sebasatiano (TU Delft - Quantum Circuit Architectures and Technology)

Affiliation
QCD/Sebastiano Lab
Copyright
© 2022 L.A. Enthoven, J. van Staveren, J. Gong, M. Babaie, F. Sebastiano
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Publication Year
2022
Language
English
Copyright
© 2022 L.A. Enthoven, J. van Staveren, J. Gong, M. Babaie, F. Sebastiano
Affiliation
QCD/Sebastiano Lab
Pages (from-to)
228-229
ISBN (electronic)
978-1-6654-9772-5
DOI:
https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830309
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Abstract

This paper presents a 15b cryo-CMOS DAC for multiplexed spin-qubit biasing implemented in a 22-nm FinFET process. The integrating-DAC architecture and the robust digitally-assisted high-voltage output stage enable a low power dissipation (157W) and small area (0.08mm2) independent of the number of biased qubits, and a 3V output range well beyond the nominal supply. This represents the first scalable solution for cryo-CMOS qubit biasing, which achieves a 1.8× better voltage resolution with a lower DNL over a 3× larger output range than the current state-of-the-art.

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