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A 3V 15b 157W Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing

Conference Paper (2022)
Author(s)

Luc Enthoven (TU Delft - QCD/Sebastiano Lab)

Job Van Staveren (TU Delft - QCD/Sebastiano Lab)

Jiang Gong

Masoud Babaie (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Fabio Sebastiano (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
QCD/Sebastiano Lab
DOI related publication
https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830309 Final published version
More Info
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Publication Year
2022
Language
English
Research Group
QCD/Sebastiano Lab
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Pages (from-to)
228-229
Publisher
IEEE
ISBN (electronic)
978-1-6654-9772-5
Event
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (2022-06-12 - 2022-06-17), Honolulu, United States
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Abstract

This paper presents a 15b cryo-CMOS DAC for multiplexed spin-qubit biasing implemented in a 22-nm FinFET process. The integrating-DAC architecture and the robust digitally-assisted high-voltage output stage enable a low power dissipation (157W) and small area (0.08mm2) independent of the number of biased qubits, and a 3V output range well beyond the nominal supply. This represents the first scalable solution for cryo-CMOS qubit biasing, which achieves a 1.8× better voltage resolution with a lower DNL over a 3× larger output range than the current state-of-the-art.

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