Special Session
STT-MRAMs: Technology, Design and Test
Anteneh Gebregiorgis (TU Delft - Computer Engineering)
Lizhou Wu (TU Delft - Computer Engineering)
Christopher Münch (Karlsruhe Institut für Technologie)
Siddharth Rao (IMEC)
Mehdi B. Tahoori (Karlsruhe Institut für Technologie)
Said Hamdioui (TU Delft - Quantum & Computer Engineering)
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Abstract
STT-MRAM has long been a promising non-volatile memory solution for the embedded application space owing to its attractive characteristics such as non-volatility, low leakage, high endurance, and scalability. However, the operating requirements for high-performance computing (HPC) and low power (LP) applications involve different challenges. This paper addresses different aspects of STT-MRAM; it will cover state-of-the-art, some new results and future challenges related to technology, design and test. While STT-MRAM devices have shown encouraging performance metrics at device-level, a key challenge has been achieving backend-of-line (BEOL) CMOS compatibility, while retaining the benefits of low power operation. Scaling demands to improve data densities have placed additional challenges in terms of addressing the impact of process-induced damage on device performance at CD < 100 nm. In addition, the paper discusses the design of reliable read mechanism considering the variability effects. Moreover, the failure of traditional fault modeling and test approaches in model STT-MRAM unique defects for appropriate test solutions is demonstrated in this paper based on silicon data.