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Sub-100-μV Cryogenic Biasing with Low-Noise Multilevel Memristors

Pt-Interface Tuning for Scalable Qubit Control

Conference Paper (2026)
Author(s)

Erbing Hua (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Stijn Heemskerk (TU Delft - Applied Sciences)

Ryoichi Ishihara (TU Delft - QID/Ishihara Lab, TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
Computer Engineering
DOI related publication
https://doi.org/10.1109/EDTM65772.2026.11497540 Final published version
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Publication Year
2026
Language
English
Research Group
Computer Engineering
Publisher
IEEE
ISBN (electronic)
9798331585983
Event
10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026 (2026-03-01 - 2026-03-04), Penang, Malaysia
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Abstract

We demonstrate Pt/HfO2/Pt/Ti/Pt memristors enabling sub-100 μV cryogenic biasing for scalable qubit control. Compared with pure Pt-based stacks, the Pt-interface-engineered lowers the effective barrier by approximately 0.3 eV, achieving bipolar switching, read-noise ≤0.32% at approximately 4.0 K. Monte-Carlo analysis confirms bias resolution < 100 μV in a six-device programmable-gain amplifier (PGA), validating that interface-engineer can path the way for cryogenic memristors-based wiring bottleneck compared with Au/Pt-based memristors for cryo-compatible analog memory applications.

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File under embargo until 09-11-2026