Dual-Loop Passive-Input Sigma–Delta Modulator
Fekry Mohamed (TU Delft - Electrical Engineering, Mathematics and Computer Science)
K.A.A. Makinwa – Mentor (TU Delft - Electrical Engineering, Mathematics and Computer Science)
T.M. Lopes Marta da Costa – Graduation committee member (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Robert van Veldhoven – Graduation committee member (NXP Semiconductors)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
This thesis presents a passive-input dual-loop continuous-time sigma–delta modulator that suppresses first-stage quantization noise in the analog domain. The proposed architecture requires only a fixed digital attenuation, avoiding a complex digital cancellation filter and dedicated calibration loop. Implemented in TSMC 65 nm CMOS, the modulator operates from a 1.2 V supply with a 100 MHz sampling frequency and an approximately 200 kHz signal bandwidth. Schematic-level simulations achieve a peak SNDR of 100.61 dB and a dynamic range of 103.66 dB while consuming 1.094 mW. RCC-extracted simulations achieve an SNR of 100 dB and an SNDR of 99.53 dB.