Lock-in Ultrafast Electron Microscopy Simultaneously Visualizes Carrier Recombination and Interface-Mediated Trapping

Journal Article (2020)
Authors

M.W.H. Garming (ImPhys/Microscopy Instrumentation & Techniques)

M. Bolhuis (Kavli institute of nanoscience Delft, TU Delft - QN/Conesa-Boj Lab)

S. Conesa Boj (Kavli institute of nanoscience Delft, TU Delft - QN/Conesa-Boj Lab)

Pieter Kruit (ImPhys/Microscopy Instrumentation & Techniques)

J.P. Hoogenboom (ImPhys/Microscopy Instrumentation & Techniques)

Research Group
ImPhys/Microscopy Instrumentation & Techniques
Copyright
© 2020 M.W.H. Garming, M. Bolhuis, S. Conesa Boj, P. Kruit, J.P. Hoogenboom
To reference this document use:
https://doi.org/10.1021/acs.jpclett.0c02345
More Info
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Publication Year
2020
Language
English
Copyright
© 2020 M.W.H. Garming, M. Bolhuis, S. Conesa Boj, P. Kruit, J.P. Hoogenboom
Research Group
ImPhys/Microscopy Instrumentation & Techniques
Issue number
20
Volume number
11
Pages (from-to)
8880-8886
DOI:
https://doi.org/10.1021/acs.jpclett.0c02345
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Abstract

Visualizing charge carrier flow over interfaces or near surfaces meets great challenges concerning resolution and vastly different time scales of bulk and surface dynamics. Ultrafast or four-dimensional scanning electron microscopy (USEM) using a laser pump electron probe scheme circumvents the optical diffraction limit, but disentangling surface-mediated trapping and ultrafast carrier dynamics in a single measurement scheme has not yet been demonstrated. Here, we present lock-in USEM, which simultaneously visualizes fast bulk recombination and slow trapping. As a proof of concept, we show that the surface termination on GaAs, i.e., Ga or As, profoundly influences ultrafast movies. We demonstrate the differences can be attributed to trapping-induced surface voltages of approximately 100-200 mV, which is further supported by secondary electron particle tracing calculations. The simultaneous visualization of both competing processes opens new perspectives for studying carrier transport in layered, nanostructured, and two-dimensional semiconductors, where carrier trapping constitutes a major bottleneck for device efficiency.