Cryogenic Interposer System for 3D Integration of Quantum Computers

Enhancing Scalability of Next-Generation Computing Solutions

Master thesis (2023)

Authors

A. Dubey Electrical Engineering, Mathematics and Computer Science

Contributors

R. Ishihara QID/Ishihara Lab - QuTech Advanced Research Centre (supervisor 1)
S. Nur QID/Ishihara Lab - QuTech Advanced Research Centre (supervisor 1)
Massimo Mastrangeli Electronic Components, Technology and Materials - EEMCS (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2023 Aryan Dubey
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Published Date

28-08-2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

Demand for high density, high bandwidth, and low power Integrated Circuits (ICs) is rapidly increasing even as Moore's Law is starting to plateau. Among the new wave of technologies that are meant to continue the prevalent trend of semiconductor device scaling, 3D System Integration promises many advantages over traditional single-planar designs. This technology enables designers to stack multiple dies and unlock new functionality by reducing the footprint of the final device package. Using 3D Integration, multiple different types of chiplets (Digital IC, Analog IC, MEMS) can be integrated into a single package, potentially bypassing an expensive move to a newer process node and unlocking even more functionality from the same package.

These downscaling issues are not limited to traditional CMOS technologies but extend to Quantum Computers. Due to the highly heterogeneous nature of Quantum ICs, and especially their requirement of low qubit decoherence noise, we require high-density connections from the Qubit layer to the Microelectronics Control layer while maintaining appropriate spacial separation between the two. In this project, the qubit layer is comprised of Diamond Colour Centers in a Photonic IC with other optical components such as SNSPDs, and MEMS switches. On the other hand, the microelectronics control layer is a Cryogenic CMOS chip.

The main goal of this project is to design an Interposer and related technologies like Through Silicon Vias (TSVs) and Microbumps to successfully integrate these two chiplets in a single 3D assembly. We conduct thermal analysis of multiple 3D assembly designs using Finite Element Modelling to derive optimum fabrication specifications. Subsequently, fabrication recipes are developed and optimised for TSV etching, coating, and patterning with superconductive sidewall liners. Recipes are also developed to fabricate Indium Microbumps using techniques like evaporation, liftoff, and atmospheric reflow. Utilizing these microbumps, we conduct cold-compression flip-chip experiments. Finally, we establish cryogenic measurement setups to electrically characterize these fabricated devices.