A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors
Joost Romijn (TU Delft - Electronic Components, Technology and Materials)
Sten Vollebregt (TU Delft - Electronic Components, Technology and Materials)
Henk W. van Zeijl (TU Delft - Electronic Components, Technology and Materials)
Pasqualina M. Sarro (TU Delft - Electronic Components, Technology and Materials)
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Abstract
In this paper we present, for the first time, the successful monolithic wafer-scale integration of CVD graphene with CMOS logic for highly miniaturized smart sensing structures with on-chip readout electronics. The use of a patterned CMOS compatible catalyst for pre-defined regions of CVD graphene growth, and the transfer-free process used, allows the direct implementation of patterned graphene structures between the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. No significant deterioration of the graphene properties and of the CMOS logic gate performance due to the high temperature graphene growth step was observed. This is a significant leap towards industrial production of graphene-based smart MEMS/NEMS sensors.