A Wafer-Scale Process for the Monolithic Integration of CVD Graphene and CMOS Logic for Smart MEMS/NEMS Sensors

Conference paper (2019)

Authors

J. Romijn Electronic Components, Technology and Materials -

S. Vollebregt Electronic Components, Technology and Materials -

H.W. van Zeijl Electronic Components, Technology and Materials -

Pasqualina M Sarro Electronic Components, Technology and Materials -

Research Group

Electronic Components, Technology and Materials () (TU Delft)

DOI

https://doi.org/10.1109/MEMSYS.2019.8870741

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Published Date

2019

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Components, Technology and Materials

Abstract

In this paper we present, for the first time, the successful monolithic wafer-scale integration of CVD graphene with CMOS logic for highly miniaturized smart sensing structures with on-chip readout electronics. The use of a patterned CMOS compatible catalyst for pre-defined regions of CVD graphene growth, and the transfer-free process used, allows the direct implementation of patterned graphene structures between the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. No significant deterioration of the graphene properties and of the CMOS logic gate performance due to the high temperature graphene growth step was observed. This is a significant leap towards industrial production of graphene-based smart MEMS/NEMS sensors.

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