A Security Verification Template to Assess Cache Architecture Vulnerabilities

Conference paper (2020)

Authors

Tara Ghasempouri Tallinn University of Technology
Jaan Raik Tallinn University of Technology
Kolin Paul Tallinn University of Technology
Cezar Reinbrecht Computer Engineering - EEMCS
S. Hamdioui Quantum & Computer Engineering
M. Taouil Computer Engineering - EEMCS
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2020 Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, S. Hamdioui, M. Taouil
DOI
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https://doi.org/10.1109/DDECS50862.2020.9095707
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Published Date

2020

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.