Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors

Conference paper (2007)

Authors

MF Snoeij Electronic Instrumentation -

A.J.P.A.M. Theuwissen Electronic Instrumentation -

J.H. Huijsing Electronic Instrumentation -

K.A.A. Makinwa Electronic Instrumentation -

Research Group

Electronic Instrumentation () (TU Delft)

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Published Date

2007

Language

Undefined/Unknown

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

The ever-increasing resolution of CMOS imagers has had a profound impact on their analog readout electronics, and, in particular, on their ADC architecture. This paper gives an overview of the development of column-parallel ADCs that enable the high-speed and power-efficient readout of high-resolution CMOS imagers. In particular, the recently proposed multiple-ramp single-slope (MRSS) ADC will be discussed.