Compact delay modeling of latch-based threshold logic gates
Conference Paper
(2002)
Author(s)
MD Padure (TU Delft - Computer Engineering)
Sorin D. Cotofana (TU Delft - Computer Engineering)
C Dan (External organisation)
Stamatis Vassiliadis (TU Delft - Computer Engineering)
M Bodea (External organisation)
Research Group
Computer Engineering
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https://resolver.tudelft.nl/uuid:944e3a4c-b4fa-47d3-9dc4-c58e53fc5cd9
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Publication Year
2002
Research Group
Computer Engineering
Pages (from-to)
317-320
ISBN (print)
0-7803-7440-1
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