Integrating a MOSFET into a c-Si IBC Solar Cell

Abstract

Several promising photovoltaic (PV) concepts are supported by transistors. Along with the growth of PV capacity in the urban environment, issues related to partial shading highlight the interest in more shade-tolerant PV systems. An example of technologies improving a PV module’s energy yield under partial shading is the submodule power optimizer, including a power converter that operates sub-module maximum power point tracking (MPPT). Alternately, reconfigurable PV modules enable dynamic reconfiguration of the solar cells’ interconnections to optimize the energy yield depending on the irradiance distribution. Both technologies make use of transistors as fundamental components. Integrating the latter into the solar cell wafer might be a solution for cost reduction and reliability improvement and thus support such concepts. Moreover, that kind of transistor integration can have applications in solar cell-embedded electronic and digital devices.

In this thesis, a lateral metal-oxide-semiconductor field-effect transistor (MOSFET) and an interdigitated back-contacted (IBC) solar cell are integrated into the same crystalline silicon (c-Si) wafer. A combined process flow is developed to manufacture both components with a minimum number of additional steps compared to single-component manufacturing processes. One criterion for this is a high similarity in the design of the device. Therefore, a tunneling oxide passivated contact (TOPCon) solar cell structure is used, involving polycrystalline silicon (poly-Si) at the device’s backside. Similarly, the MOSFET’s gate is made of a highly doped poy-Si film. Ion implantation is used as a common doping process.

Both solar cells and transistors that were manufactured with the combined process flow are first characterized separately. The highest efficiencies obtained for n-type and p-type solar cells are 20.29% and 20.66%, respectively. This is achieved thanks to multiple combined passivation approaches including TOPCon, wet poly-Si etching, a front-side hydrogenated amorphous silicon (a-Si:H) film, and hydrogenated silicon nitride on both sides of the device. Different MOSFET layouts are explored to make the device able to handle relatively large currents. It is found that introducing several drain-source pairs in parallel is more efficient than increasing the channel width to reduce the on-resistance. The on-resistance is further minimized with a gate length reduction and wet chemical poly-Si etching. As expected, the comparison of PMOS and NMOS (MOSFETs built on n-type and p-type wafers, respectively) shows better on-performance for the latter. A minimum on-resistance value of 1 Ω is then obtained. However, a higher leakage current consistently seems to come along with reduced on-resistance; i.e., higher on-performance is coupled with lower off-performance. Finally, experiments are performed combining both components. Under illumination, the MOSFET exhibits lower off-performance due to the photovoltaic effect. However, this effect does not affect the on-performance of the component. The monolithically connected components exhibit I-V characteristics that depend on the applied MOSFET’s gate potential. In the on-mode, the solar cell maintains more than 95% of the conversion efficiency compared to the efficiency measured with the same solar cell without the transistor. However, a non-zero current is obtained in the off-mode, exhibiting low transistor blocking capability. Nevertheless, the large difference in characteristics obtained between the on- and off-modes proves the feasibility of integrating a solar cell and a transistor on the same substrate with a minimum number of additional processing
steps.