Silicon is a promising alternative to the conventional graphite anodes due to its high theoretical capacity and favorable lithiation potential for lithium-ion batteries (LIBs) with liquid as well as solid-state electrolytes. However, lithiation-induced extreme volume change causes severe mechanochemical deformation and continuous formation of solid-electrolyte interphase leads to cell failure. One of the strategies to mitigate this problem is alloying silicon with a suitable element that can alter the surface electrochemistry and/or lithiation pathways, and acts as mechanical buffer. Nonetheless, these benefits come with a compromise on the specific capacity, which strongly influences the mass loading of the electrodes, highlighting the need to deconvolute the intertwined influence of composition and mass loading when designing high performance electrodes. In this work, we systematically studied the influence of composition and mass loading in monolithic amorphous silicon and non-stoichiometric silicon nitride (SiN_x) electrodes on their electrochemical performance as LIB anodes. The incorporation of nitrogen in the electrode matrix clearly improves the electrochemical stability at the expense of reduced specific capacity, while higher mass loading accelerates capacity fading, most critically in amorphous silicon electrodes. Postmortem analysis reveals that such capacity fading in the electrodes with higher mass loading can be related to delamination due to evolved tensile stress during the charge–discharge cycle. Yet, nitrogen-rich SiN_x monolithic electrodes accommodate strain more effectively. These findings demonstrate that while pristine Si delivers high specific capacity and long-term stability in thin films, thicker (>1 µm) monolithic electrodes benefit from higher nitrogen content in SiN_x, which provides more stable cycling and sustained capacity.

A major challenge in multijunction devices is reduced light incoupling caused by interference fringes from optical microcavities. This paper reports a potential route to mitigate the interference effects with an effective front-window design. The concepts of interface scattering and grain scattering are implemented at the front side of superstrate tandem solar cells. A random texturing and periodic-hexagonal texturing approach on glass is used as interface scatterers. However, applying an interface scatterer alone is insufficient to eliminate the interference effects of optical cavities completely. Use of sputtered unintentionally doped zinc oxide (i-ZnO) or tin oxide (SnO) as grain scatterers stacked over random and periodic glass textures quenches the interference effects significantly. For a random textured glass substrate, a 1.5-μm thick i-ZnO layer could quench interference in the top cell, except for the effect of the optical cavity formed in the amorphous top cell. Hexagonal craters on glass, combined with a 0.9-μm thick i-ZnO layer, effectively mitigate fringes formed by all optical cavities in the device. This sample demonstrates the highest incoupled photon flux with 86% of photons entering the device. Use of a wide-bandgap grain scatterer, such as SnO, reduces parasitic absorption of high-energy photons while mitigating optical cavities. The design principles discussed in this work can be applied to any thin-film multijunction solar cells consisting of layers with contrasting refractive indices.

Periodic hexagonal microtexture arrays (also known as honeycombs) are successfully implemented for the first time in a superstrate glass configuration. Hexagonal textures on glass demonstrate an anti-reflective effect when compared to flat glass. It is shown that light scattering increases at the honeycomb interfaces with an increase in texture height and periodicity. The performance of the textures is demonstrated using thin-film single-junction PV devices based on an indirect bandgap semiconductor material, nanocrystalline silicon (nc-Si:H), which requires light trapping in the infrared region of the spectrum. Inspecting the nc-Si:H bulk absorber suggests a conformal, crack-free growth of crystals on the hexagonal arrays. Short-circuit current density (J_SC) increases with an increase in the aspect ratio of the superstrate, without compromising voltage and fill factor. The J_SC enhancement is attributed to a combined benefit of (i) the anti-reflective nature of developed textures, (ii) trapping light within the absorbing layer through multiple order diffraction at the front and (iii) reflection from a back reflector with adapted hexagonal morphology. With the above observations, a J_SC of 28.6 mA/cm² (photovoltaic conversion efficiency of 9.3 %) is achieved for a 5μm periodic texture with a height of 1μm (aspect ratio = 0.21). This is the highest reported J_SC for a single-junction nc-Si:H solar cell in a superstrate configuration without an external anti-reflection coating.

Techniques to facilitate excellent optical yield are required to manufacture high-performing solar cells. In thin-film solar cells, light scattering with the help of textured interfaces increases the absorption path length of photons and reduces the reflection of the photovoltaic active layer. These textures should also facilitate the growth of crack-free thin-film layers, ensuring high efficiency in multijunction devices. This work explores three texturing methods for glass that have the potential to be integrated into solar cells in a superstrate configuration. A detailed study of sacrificial texturing on glass using i-ZnO ((Formula presented.)) and indium-doped tin oxide ((Formula presented.)) is presented. The optical interaction of these textures is correlated to their root-mean-square (RMS) roughness ((Formula presented.)). It is demonstrated that high optical scattering can be achieved for both (Formula presented.) and (Formula presented.) but at different (Formula presented.) regimes. A novel texture with superimposed morphology, named superimposed sacrificial texturing ((Formula presented.)), is created by combining (Formula presented.) and (Formula presented.) through sequential wet etching. The (Formula presented.) exhibits exceptional transmission and light scattering properties. Nanocrystalline silicon (nc-Si:H) single-junction solar cells were fabricated in a superstrate configuration to investigate the impact of these textures on indirect bandgap thin-film solar cells. The efficiency of solar cells on (Formula presented.) is nearly 0.57% and 1.52% (absolute) more than (Formula presented.) and (Formula presented.) solar cells, respectively. By superimposing two textures, solar cells can combine the advantages of enhanced optical performance with high-quality nc-Si:H material growth.

Textured glass is used in a wide range of applications to improve optoelectrical performances, such as photovoltaics, biosensing, microfluidics, and photonics. Honeycomb textures have demonstrated an excellent performance in optical devices using crystalline silicon wafers as opaque substrates. As a pathway to translate these advantages to configurations implementing glass, hexagonal-shaped microsized craters (honeycombs) are made on glass in this study. We use photolithography combined with wet etching for this process. The relationship between photoresist mask design, glass–photoresist adhesion, wet-etching steps, and the mechanism of honeycomb formation is studied. It is demonstrated that the higher the isotropic nature of etching achieved, the deeper the hexagonal craters will be. The potential of hexagonal textures on glass to significantly reduce reflection to <8% over the entire spectral range is observed. Finally, hexagonal microsized textures with 5 μm periodicity and 1.01 μm depth that effectively diffuse 50% of the total transmitted light at near-infrared (1100 nm) wavelengths are developed.

A thorough understanding of the small-signal response of solar cells can reveal intrinsic device characteristics and pave the way for innovations. This study investigates the impedance of crystalline silicon PN junction devices using TCAD simulations, focusing on the impact of frequency, bias voltage, and the presence of a low–high (LH) junction. It is shown that the PN junction exhibits the behavior of a parallel resistor–capacitor circuit (RC-loop) with fixed element values at low frequencies, but undergoes relaxation in both resistance R_j and capacitance C_j as frequency increases. Moreover, it is revealed that the addition of a LH junction impacts the impedance by altering R_j, C_j, and the series resistance R_s. Finally, while various publications on solar-cell impedance model the LH junction using an RC-loop, the findings in this study indicate that such a model does not accurately represent the underlying physics. Instead, this approach is likely compensating for the frequency-dependent behavior of R_j and C_j.

Nowadays, an increasing share of photovoltaic (PV) systems makes use of module- or submodule-level power electronics (PE). Furthermore, PE is used in stand-alone devices powered by PV-storage solutions. One way to facilitate further implementation of PE in PV applications is to integrate PE components into crystalline silicon PV cells. Herein, the COSMOS device is introduced, denoting COmbined Solar cell and metal-oxide-semiconductor field-effect transistor (MOSFET). Specifically, the combined manufacturing of lateral power MOSFETs and interdigitated back contact solar cells with tunnel-oxide passivated contacts (TOPCon) on a single wafer is reported. Many steps of the proposed process flow are used for the fabrication of both devices, enabling cost-effective integration of the MOSFET. Both n-type solar cells with integrated p-channel MOSFETs (PMOS) and p-type solar cells with integrated n-channel MOSFETs (NMOS) are successfully manufactured. NMOS devices perform better in achieving low on-resistance, while PMOS devices exhibit lower leakage currents. Furthermore, the study reveals integration challenges where off-state leakage currents of the MOSFET can increase due to illumination and specific configurations of monolithic interconnections between the MOSFET and the solar cell. Nevertheless, for both n-type and p-type solar cells, efficiencies exceeding 20% are achieved, highlighting the potential of the proposed process for COSMOS devices.

Passivating contacts are crucial for realizing high-performance crystalline silicon solar cells. Herein, contact formation by plasma-enhanced chemical vapor deposition (PECVD) followed by an annealing step is focused on. Poly-SiO_x passivating contacts by combining plasma-assisted N₂O-based oxidation of silicon (PANO-SiO_x) with a thin film of phosphorus (n⁺) or boron (p⁺)-doped hydrogenated amorphous silicon oxide (a-SiO_x:H) are manufactured. Postannealing is conducted for transitioning a-SiO_x:H into poly-SiO_x. The aim is to achieve a contact with low absorption and high-quality passivation. It is demonstrated that by tuning the plasma oxidation process time and power, the PANO-SiO_x thickness and its passivation quality can be controlled. A higher SiO₂ content is observed in PANO-SiO_x than in the nitric acid oxidation of silicon (NAOS-SiO_x) counterpart. PANO-SiO_x acts as a stronger diffusion barrier for both boron and phosphorus atoms compared to NAOS-SiO_x, affecting the dopant distribution during annealing. Implied open-circuit voltages up to 751 and 710 mV for n⁺ and p⁺ flat symmetric samples, respectively, are demonstrated. With respect to standard thermally grown SiO₂ tunneling oxide combined with (in/ex)situ-doped low-pressure chemical vapor deposition poly-Si, this study presents a simple alternative for manufacturing passivating contact fully based on PECVD processes.

In this article, we investigate the passivation quality and electrical contact properties for samples with a 150 nm thick n+ polysilicon layer in comparison to samples with a phosphorus diffused layer. High level of passivation is achieved for the samples with n+ polysilicon layer and an interfacial oxide underneath it. The contact properties with screen-printed fire-through silver paste are excellent (no additional recombination from metallization and specific contact resistivity (ρc) ≤ 2 mΩ·cm2) for the samples with the polysilicon layers. Fast-firing peak temperature was varied during the contact formation process; this was done to see the trend in the contact properties with the change in the thermal budget. The differences in the J0met and ρc for the two different kinds of samples are explained with the help of high-resolution scanning electron microscope imaging. Finally, we prepare M2-sized n-passivated emitter rear totally (PERT) diffused solar cells with a 150 nm thick n+ polysilicon based passivated rear contact. The best cell achieved an efficiency of 21.64%, with a Voc of 686 mV and fill factor of 80.2%.

Passivated contact based on a thin interfacial oxide and a highly doped polysilicon layer has emerged as the next evolutionary step to increase the efficiencies of industrial silicon solar cells. To take maximum advantage from this layer stack, it is vital to limit the losses at the metal polysilicon interface, which can be quantified as metal polysilicon recombination current density (J _0met) and contact resistivity. In cell concepts, wherein a large variety of silicon substrate surface finish can be obtained, it is essential to know how the surface finish affects the J _0met and contact resistivity. Herein, commercially available fire through silver paste and the metal-polysilicon recombination current densities and contact resistivity are used for three different silicon substrate surface finishes, namely: planar or saw damage etched (SDE), chemically polished in acidic solution and alkaline pyramidal textured. Contact resistivity values below 3 mΩ cm² with J _0met in order of the recombination current density of the doped region (J _0pass) are obtained for samples with planar surface for both 150 and 200 nm n⁺ polysilicon layer thicknesses. The results presented in this work show that the samples with flat substrate morphology outperform the samples with textured surfaces.

This work investigates how the thickness of the polysilicon layer and temperatures during contact sintering influence the properties of SiO_x/polysilicon passivated contacts. The n⁺ polysilicon layers deposited by low-pressure chemical vapor deposition (LPCVD) on top of a thin wet chemically grown interface oxide layer providing chemical and field-effect passivation on n-type monocrystalline silicon wafers are investigated. Three different polysilicon layer thicknesses of 50, 100, and 150 nm are considered in this work. A high level of passivation with implied V_oc values above 735 mV and J₀₁ below 5 fA cm⁻² is obtained for symmetric lifetime test samples. These samples are used to investigate the interaction of the silver paste with the polysilicon layer at different fast firing peak temperatures. Reduction in polysilicon layer thickness leads to an increase in contact resistivity as well as in J_0met. Excellent J_0met values of the order of J₀₁ with contact resistivity values below 2 mΩ cm² are obtained for samples with polysilicon layers of 100 and 150 nm thickness.

We have metallised n+ polysilicon passivated layer structures deposited by Low Pressure Chemical Vapor Deposition (LPCVD) with silver pastes. We analysed recombination at the metal contacts by photoluminescence imaging of metallised lifetime samples and found for the best paste, metal semiconductor recombination current density values (J0met) below 70 fA/cm², with contact resistivity below 2 mΩcm². To our knowledge, these are among the lowest values reported so far for full size M2 wafers with 150 nm thin polysilicon layer and wet chemical thin oxide. We also studied the effect of the peak firing temperature on the J0met and contact resistivity in this work. Further, we performed Scanning Electron Microscopy to further understand the silver polysilicon interface.

We have printed firing through silver paste on n+ polysilicon passivated layer structures deposited by Low Pressure Chemical Vapor Deposition (LPCVD). We analysed recombination at the metal contacts by photoluminescence imaging of metallised lifetime samples and found for the best paste, metal semiconductor recombination current density values (J0met) below 100 fA/cm². To our knowledge, these are among the lowest values reported so far for full size M2 wafers with 150 nm thin polysilicon layer. On samples metallised with standard commercial pastes for diffused emitters, we observed higher J0met values, while contact resistivity was acceptable for all samples. We also studied the effect of the peak firing temperature on the J0met and contact resistivity in this work. Further, we compared the impact of deep and shallow doping profiles on the passivation and the J0met values.