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A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS

Conference Paper (2021)
Author(s)

Jun Feng (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Mohammadreza Beikmirza (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Mohammadreza Mehrpoo (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Leo C.N. de Vreede (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Morteza S. Alavi (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
Electronics
DOI related publication
https://doi.org/10.1109/ISOCC53507.2021.9613887 Final published version
More Info
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Publication Year
2021
Language
English
Research Group
Electronics
Article number
9613887
Pages (from-to)
41-42
ISBN (print)
978-1-6654-0175-3
ISBN (electronic)
978-1-6654-0174-6
Event
2021 18th International SoC Design Conference (ISOCC) (2021-10-06 - 2021-10-09), Hybrid at Jeju Island, Korea, Republic of
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Abstract

We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C2MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10-12 with a 60.9-ps eye width.

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