A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS
Y.J. Feng (TU Delft - Electronics)
M. R. Beikmirza (TU Delft - Electronics)
Milad Mehrpoo (TU Delft - Electronics)
Leonardus Cornelis Nicolaas de Vreede (TU Delft - Electronics)
M.S. Alavi (TU Delft - Electronics)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C2MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10-12 with a 60.9-ps eye width.