YF
Y.J. Feng
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1
Conference paper
(2021)
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Jun Feng, Mohammadreza Beikmirza, Mohammadreza Mehrpoo, Leo C.N. de Vreede, Morteza S. Alavi
We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C2MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10-12 with a 60.9-ps eye width.
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We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C2MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10-12 with a 60.9-ps eye width.