CIM-FI

Abstract

Deep Neural Networks (DNNs) have been dominating the landscape of Artificial Intelligence (AI) applications in edge computing for several years, pushing developers to optimize architectural approaches and address power consumption concerns. Identifying memory transfers as the key contributor to the energy consumption of these workloads has led to the creation of architectures like Compute-In-Memory (CIM), bringing computation close to the storage, and thus eliminating the continuous data transfer overhead. However, reliability issues due to the environmental setting, device wear-out and operating conditions pose a significant challenge for such architectures as traditional approaches such as ECC are not adequate. To this end, we present CIM-FI, a hardware (HW) aware framework for injecting faults and analyzing the error resilience of modern DNNs on digital CIM (DCIM) accelerators. We present three diverse fault models related to DCIM soft errors, aging, and voltage scaling. The behavior of DCIM components is characterized using EDA tools and bit-level perturbations are injected into the weights and feature maps of DNNs at compile- and run-time. We test our model on three DNNs, including a Vision Transformer (ViT) and two Convolutional NNs (CNNs) and provide detailed analyses of the dependence between fault mechanism, target network and DCIM size. Our results show the interplay among these factors, the impact on accuracy and the necessity of HW-aware modeling in predicting unwanted drops in inference quality.