Cryogenic DAC for the Biasing of Spin Qubits

Abstract

Disruptive changes in the fields ofcryptography and quantum chemistry can be achieved through quantum computing,as specific computations can be sped up significantly. Thousands to millions ofqubits are required to perform these computations, illustrating the need forlarge quantum computers. These qubits must be cooled to cryogenic temperaturesin order to operate. Currently operations on few qubits can be done, these arecommonly controlled with room temperature equipment. However as the number ofqubits becomes larger, scalable and integrated electronics is required toreduce the interconnect. This has promoted research in cryogenic electronicsthat can be located close to the qubits. This thesis presents a low power,scalable cryogenic DC biasing solution for the biasing of spin qubits. Thepresented DC-DAC has been implemented in the Intel 22-nm finFET process. Unlikeconventional DACs, the designed DC-DAC periodically generates all possiblevoltages in the full scale output voltage range, and drives a multiplexer thatconnects a sample and hold capacitors when the right bias voltage for theelectrode has been generated. The DAC is able to achieve a high resolution of 16bits with low noise performance by using an offset-compensated switched capacitorintegrator. By offering a DC input to the integrator the full scale outputvoltage range can be generated, while using the offset-compensated switchedcapacitor integrator allows reduction of offset and 1/f noise which are expectedto degrade at cryogenic temperatures. The DC-DAC is designed to meet a largevoltage output range of 3 V, which breaks compliance with the nominal 1.8 Vcompliance of the thick oxide transistors in the process. While it is possibleto put larger voltages over the transistors, it is currently unknown how thiswill affect the reliability and behavior of the thick oxide transistors.Therefore, a two-stage amplifier has been implemented where the second stageuses a supply of 3.6 V. The voltage compliance in the second stage isguaranteed through cascode transistors that are dynamically biased byadditional DACs. As the addition of the second stage of the amplifier andcoarse DACs introduce another voltage domain, additional circuitry such aslogic level shifters, diode stacks and cascode transistors have been added toensure that voltage compliance is throughout the entire DAC. The DC-DACachieves a LSB step of 45.1휇푉,, avoltage output range of 3 푉,,integrated noise of 17 휇푉 rms and dissipates a total of 187휇푊, whilenot consuming more than 0.078 푚푚,2. Thehigh resolution, large voltage output range and low power of the DAC enableintegration of the DAC with the qubits, paving the way for scalable quantumcomputers.