Towards Programmable Computing-in-Memory Accelerators
Design of a general purpose programming model
T. MALIAPPIS (TU Delft - Electrical Engineering, Mathematics and Computer Science)
G. Gaydadjiev – Mentor (TU Delft - Computer Engineering)
K.G. Langendoen – Graduation committee member (TU Delft - Embedded Systems)
M. Naderan-Tahan – Mentor (TU Delft - Computer Engineering)
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Abstract
For a very long period of time, computing could meet the increasing demands of different applications due to the continued downscaling of transistors, which allowed data to be processed at a higher frequency. In the early 2000s, predictions about the physical limits and rising costs of continued down scaling prompted researchers to adopt alternative techniques to sustain performance improvements beyond frequency scaling. Among these, the most prevalent technique was the extraction and utilization of parallelism, which successfully extended performance scaling for more than a decade but has since begun to stagnate. Today, experts agree that specialized complementary hardware is crucial for further advancements. Computing-in-memory (CIM) accelerators are gaining traction as an innovative solution to the problems conventional computing is facing. While most CIM research is directed towards device, circuit, and architectural level challenges, it is also important to consider the challenges at the programming level. In this chapter, we first discuss the motivation behind CIM accelerators and why developing a programming model for them is essential. Next, we provide an overview of the challenges associated with developing a dedicated programming model for this emerging technology. Finally, we will outline the research direction of this thesis.