2-output spin wave programmable logic gate

Conference Paper (2020)
Author(s)

Abdulqader Mahmoud (TU Delft - Computer Engineering)

Frederic Vanderveken (IMEC)

Christoph Adelmann (IMEC)

F. Ciubotaru (IMEC)

SD Cotofana (TU Delft - Computer Engineering)

Said Hamdioui (TU Delft - Quantum & Computer Engineering)

Research Group
Computer Engineering
Copyright
© 2020 A.N.N. Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, S.D. Cotofana, S. Hamdioui
DOI related publication
https://doi.org/10.1109/ISVLSI49217.2020.00021
More Info
expand_more
Publication Year
2020
Language
English
Copyright
© 2020 A.N.N. Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, S.D. Cotofana, S. Hamdioui
Research Group
Computer Engineering
Pages (from-to)
60-65
ISBN (print)
978-1-7281-5776-4
ISBN (electronic)
978-1-7281-5775-7
Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Abstract

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing {AND, OR, NAND, NOR} and {XOR and XNOR} functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.

Files

License info not available