Measurement and Quantitative Analysis of Oxide Trap Evolution in Power SiC Devices

Abstract

This work proposes a nondestructive framework to track the time- and depth-resolved evolution of oxide traps in 4H-SiC metal-oxide-semiconductor (MOS) structures during time-dependent dielectric breakdown (TDDB) stress. The approach combines time-resolved gate admittance measurements with a distributed oxide admittance model and frequency-temperature depth mapping to reconstruct the measured dispersion at flatband voltage and recover nonuniform oxide trap profiles without imposing an a priori spatial distribution. Applied to long duration negative-bias TDDB, the extracted profiles reveal a strongly depth-nonuniform and field-accelerated defect build-up: higher stress not only increases the trap population, but also broadens the active defect region deeper into the oxide as breakdown is approached. By tracking the average trap density and the centroid of oxide trapped charge in the probed oxide region, we quantify the spatial evolution and relate it to the concurrent transients in gate leakage current, flatband voltage shift, and increment of interface trap density, without relying on destructive techniques, such as transmission electron microscopy, thus preserving the device for continuous evaluation. The same methodology is further demonstrated on stressed silicon carbide (SiC) power mosfets, supporting device-level relevance and providing a workflow for depth-resolved characterisation of SiC gate oxide degradation under negative stress.