Robust design of a low-OSR continuous-time pipeline ADC

Abstract

A continuous-time pipeline (CTP) analog-to-digital converter (ADC) consists of a number of cascaded stages, each employing a coarse ADC to digitize the residue signal generated by the previous stage. Compared to a continuous-time sigma-delta ADC, a CTP-ADC offers high bandwidth with relatively low sampling rates.

Due to the image signals produced by the coarse ADC, CTP-ADCs are easily saturated by input signals near integer multiples of the sampling frequency (k·Fs). In addition, the amplitude of the residue signal at the output of their first stages is sensitive to process variation. In this work, the delay line, employed to match the phase shift between different paths of a CTP-ADC, is a second-order all-pass filter (APF), while the coarse ADC is a first-order continuous-time sigma-delta modulator (CTMOD1). Together, these techniques improve near-Fs residue suppression by at least 6 dB and in-band residue suppression by 3.5 dB.

A transistor-level implementation of the CTMOD1 was made in 28nm CMOS. It consists of a 4-bit resistive DAC (RDAC), a 4-bit quantizer, and an active-RC integrator. It achieves 27 dB SNDR, -53 dB SFDR, and consumes 3.3 mW. Compared to an earlier coarse ADC design, which required 4-bit dither to mitigate in-band spurs, it requires only 1-bit dither.