A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme
Hui Jiang (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Costantino Ligouras (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Stoyan Nihtianov (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Kofi Makinwa (TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.