Mitigation of sense amplifier degradation using input switching

Conference paper (2017)

Authors

D.H.P. Kraak Computer Engineering - EEMCS
I.O. Agbo Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS
S. Hamdioui Computer Engineering - EEMCS
Pieter Weckx Katholieke Universiteit Leuven, IMEC
Francky Catthoor IMEC, Katholieke Universiteit Leuven
Wim Dehaene Katholieke Universiteit Leuven
Research Group
Computer Engineering (EEMCS) (TU Delft)
Mitigation Offset voltage Zero-time variability Run-time variability SRAM sense amplifier Sensing delay
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Published Date

2017

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worst-case scenarios are considered, which will not present the actual workload of the targeted application. Alternatively, mitigation schemes can be used to counteract the variability. This paper presents a run-time design-for-reliability scheme for memory Sense Amplifiers (SAs); SAs are an integral part of any memory system and are very critical for high performance. The proposed scheme mitigates the impact of time-dependent variability due to aging by using an on-line control circuit to create a balanced workload. The simulation results show that the proposed scheme can reduce the most critical figures-of-merit, namely the offset voltage shift and the sensing delay of the SA with up to ~40% and ~10%, respectively, depending on the stress conditions (temperature, voltage, workload).

Files

07927107.pdf
(.pdf | 0.233 Mb)