PW
Pieter Weckx
Authored
19 records found
ESRAM Reliability
Why is it still not optimally solved?
As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has ma
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Device aging
A reliability and security concern
Device aging is an important concern in nanoscale designs. Due to aging the electrical behavior of transistors embedded in an integrated circuit deviates from original intended one. This leads to performance degradation in the underlying device, and the ultimate device failure. T
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Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation sc
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Designers typically add design margins to compensate for chip aging. However, this leads to yield loss (in case of overestimation) or low reliability (in case of underestimation). This paper analyzes the impact of aging on a complete high-performance industrial 14-nm FinFET SRAM.
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This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of a memory sense amplifier design using
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Designers typically add design margins to semiconductor memories to compensate for aging. However, the aging impact increases with technology downscaling, leading to the need for higher margins. This results into a negative impact on area, yield, performance, and power consumptio
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To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins
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Nowadays, typical (memory) designers add design margins to compensate for uncertainties, however, this may be overestimated leading to yield loss, or underestimated leading to reduced reliability designs. Accurate quantification of all uncertainties is therefore critical to provi
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The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amp
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Designers typically add design margins to compensate for time-zero variability (due to process variation) and time-dependent (due to, e.g., bias temperature instability) variability. These variabilities become worse with scaling, which leads to larger design margin requirements.
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Memory designs typically contain design margins to compensate for aging. As aging impact becomes more severe with technology scaling, it is crucial to accurately predict such impact to prevent overestimation or underestimation of the margins. This paper proposes a methodology to
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With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). This paper presents a comparative study of the BTI impact while considering varying supply voltages and temperatures for three me
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Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFE
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This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technol
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Bias Temperature Instability (BTI) has become a major reliability challenge for nano-scaled devices. This paper presents BTI analysis for the SRAM write driver. Its evaluation metric, the write delay (WD), is analyzed for various supply voltages and temperatures for three technol
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This paper investigates the impact of aging in the read path of 32nm high performance SRAM; it combines the impact on the memory cell, on the sense amplifier, and on the way they interact. The analysis is done while considering different workloads and by inspecting both the bit-l
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