Comparative BTI Analysis for Various Sense Amplifier Designs

Conference paper (2016)

Authors

I.O. Agbo Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS
S. Hamdioui Computer Engineering - EEMCS
Pieter Weckx IMEC, Katholieke Universiteit Leuven
P Raghavan IMEC
Francky Catthoor IMEC, Katholieke Universiteit Leuven
Research Group
Computer Engineering (EEMCS) (TU Delft)
NBTI BTI SRAM sense amplifier PBTI
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Published Date

2016

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). This paper presents a comparative study of the BTI impact while considering varying supply voltages and temperatures for three memory sense amplifier (SA) designs: low power (LP), mid power/performance (MP), and high performance (HP). As an evaluation metric, the sensing delay (SD) of the three designs is analyzed for various workloads using 45nm technology. The results show that HP SA degrades faster than MP SA and LP SA irrespective of the workload, supply voltage, and temperature. At nominal supply voltage and temperature, HP degrades up to 1.62x faster than MP, and up to 1.94x faster than LP designs for the worst case workload. In addition, the results show that an increase of 10% in power supply has a marginal impact on the relative degradation. In contrast, the results show that a temperature increment significantly worsens the BTI impact. Finally, the results show that for 16nm technology, BTI impact becomes worse and even causes read failures. This clearly indicates that designing for reliability is not only strongly application dependent, but also technology node dependent. Hence, one has to carefully consider the targeted application, design, and technology node in order to provide appropriate solutions.