Neural network partitioning for resource-limited environments
P. Geel (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Zaid Al-Ars – Mentor (TU Delft - Computer Engineering)
Nick van der Meijs – Coach (TU Delft - Signal Processing Systems)
J. Petri-König – Graduation committee member (AMD)
Kevin McElligott – Coach (Alten)
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Abstract
The demand for implementing neural networks on edge devices has rapidly increased as they allow designers to move away from expensive server-grade hardware. However, due to the limited resources available on edge devices, it is challenging to implement complex neural networks. This study selected the Kria SoM KV260 hardware platform due to its affordability and sufficient hardware capabilities for creating a resource-constrained environment. By leveraging the hardware acceleration capabilities of the FPGA for specific nodes of the MobileNetv1 model and offloading other nodes to the onboard quad-core ARM cortex-A53 CPU, it was feasible to implement a neural network on a hybrid combination of CPU and FPGA. Results showed that when executing the MobileNetv1 model in a hybrid configuration, a total runtime improvement of 2.8x over a pure CPU implementation can be achieved. The study concludes that node-wise partitioning of the MobileNetv1 model is a practical solution. This approach offers a cost-effective solution for users who seek an accessible way to run neural networks without the need for expensive server-grade hardware.