A CMOS image sensor with a column-level multiple-ramp single-slope ADC

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A CMOS image sensor with a column-level multiple-ramp single-slope ADC

Conference Paper (2007)

Author(s)

MF Snoeij (TU Delft - Electronic Instrumentation)

P Donegan (External organisation)

A.J.P.A.M. Theuwissen (TU Delft - Electronic Instrumentation)

Kofi A.A. Makinwa (TU Delft - Electronic Instrumentation)

Johan H. Huijsing (TU Delft - Electronic Instrumentation)

Research Group

Electronic Instrumentation

DOI related publication

https://doi.org/10.1109/ISSCC.2007.373516

To reference this document use:

https://resolver.tudelft.nl/uuid:fbc90765-5960-4d50-9f8a-3cb2fbe4f1ff

More Info

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Publication Year

2007

Research Group

Electronic Instrumentation

Pages (from-to)

1-4

ISBN (print)

1-4244-0853-9

Abstract

A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.

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