Print Email Facebook Twitter A Subthreshold Source-Coupled Logic based Time-Domain Comparator for SAR ADC based Cardiac Front-Ends Title A Subthreshold Source-Coupled Logic based Time-Domain Comparator for SAR ADC based Cardiac Front-Ends Author Rout, S. (TU Delft Bio-Electronics) Babayan-Mashhadi, Samaneh (Eindhoven University of Technology) Serdijn, W.A. (TU Delft Bio-Electronics) Date 2019-11-01 Abstract Low-voltage and low-power front-end design is required for the safe and long-term monitoring of cardiac signals. To address the low-voltage challenge, this paper presents a subthreshold source-coupled logic (STSCL) based time-domain comparator designed in 180 nm CMOS process technology. At a low supply voltage of 0.8 V, the STSCL time-domain comparator consumes 2.3 μW at 1 MHz. Using 4 stages, the input referred noise and the offset of the comparator are 32 μVrms and 1.8 mV, respectively. Subject biosignal acquisitionlow-voltagesource-coupled logictime-domain comparator To reference this document use: http://resolver.tudelft.nl/uuid:1e6f9ed2-d2d3-41ce-aaff-c3f6b39cc283 DOI https://doi.org/10.1109/APCCAS47518.2019.8953136 Publisher IEEE ISBN 9781728129402 Source Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption Event 15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019, 2019-11-11 → 2019-11-14, Bangkok, Thailand Series Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption Part of collection Institutional Repository Document type conference paper Rights © 2019 S. Rout, Samaneh Babayan-Mashhadi, W.A. Serdijn Files PDF APCCAS2019_srout_authorsu ... mitted.pdf 1.07 MB Close viewer /islandora/object/uuid:1e6f9ed2-d2d3-41ce-aaff-c3f6b39cc283/datastream/OBJ/view