A Novel Neural Recording IC with Adaptive Gain Control for Wide-Dynamic Range Closed-Loop Neural Interfaces

A Novel Neural Recording IC with Adaptive Gain Control for Wide-Dynamic Range Closed-Loop Neural Interfaces

Zhang, Remy (TU Delft Electrical Engineering, Mathematics and Computer Science)

Muratore, D.G. (mentor)
Abdelgaliel, B.H.B.M. (mentor)
Du, S. (graduation committee)

Delft University of Technology

Electrical Engineering

2023-10-23

Bidirectional neural recording ICs faces the challenge of simultaneous stimulation and recording. The recording IC should endure large stimulation artifacts while capturing weak neural signals excited by the stimuli. The stimulation artifacts can be as large as hundreds of millivolts, which can saturate the recording front end. Conventional neural-recording ICs use a low-noise-amplifier (LNA), a programmable-gain amplifier (PGA) followed by an analog-to-digital converter (ADC), leading to low power consumptions and great noise performances. However, the dynamic range (DR) is usually limited to 50 dB. State-of-the-art recording ICs using direct-conversion ADCs have been intro- duced to increase the DR. However, the typical power and area consumption for these architectures are exceeding the requirements for next-generation brain-computer interfaces. This work proposes a novel neural-recording IC system architecture with satu- ration prevention in presence of large stimulation artifacts. The proposed architecture consists of an AC-coupled boxcar sampler, switched-capacitor low-pass filter followed by a 10-bit asynchronous SAR ADC. The integrated voltage at the output of the boxcar sampler is sampled by the ADC and monitored by a level-cross detection block. Based on the output of the level-cross detection block, the integration time, and thus the gain, can be tuned to different configurations pre-defined in a look-up table (LUT). The additional noise penalty due to noise-folding from decreasing the integration time is compensated by oversampling and averaging. The proposed system architecture is partially imple- mented at transistor level while the ADC and digital blocks are modeled using verilog-A as a proof-of-concept. The analog front-end achieves a DR of 69.5 dB with a peak-to-peak maximum input amplitude of 180 mVPP and a typical ENOB of 8.01 bits.

Bidirectional neural interfaces
Artifact mitigation
Wide dynamic range
Boxcar sampler
ADC
Adaptive Gain
OTA
Saturation prevention

http://resolver.tudelft.nl/uuid:9dc46e2e-cfad-4ae6-97fc-448c7a8006ba

Student theses

master thesis

© 2023 Remy Zhang