Design of a DAC-based Cryo-CMOS 51.2 Gb/s PAM4 Wireline Transmitter

Master thesis (2021)

Authors

N.E. Fakkel Electrical Engineering, Mathematics and Computer Science

Contributors

M. Babaie Electronics - EEMCS (supervisor 1)
F. Sebastiano Quantum Circuit Architectures and Technology - EEMCS (supervisor 2)
L.C.N. de Vreede Electronics - EEMCS (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2021 Niels Fakkel
Transmitter Cryo-CMOS DAC PAM4 Wireline
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Published Date

14-10-2021

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

With the current advancements in quantum computing moving more circuitry into the cryogenic chamber there is a need for high-speed connectivity between the cryogenic and room temperature environment. Studies conducted to date have achieved high-speed links of multiple Gb/s utilizing a single CMOS chip at room temperature, yet a Cryo-CMOS wireline transmitter addresses a new topic in high-speed cryogenic electronic design necessary for the functioning and scale-up of quantum computers. This thesis entails the design of A DAC-based Cryo-CMOS 51.2 Gb/s PAM4 Wireline Transmitter. Overall, the proposed design is meant to demonstrate a high-speed signal generated by a Cyro-CMOS chip can be send through a cable from a cryogenic environment and received at room temperature. Requirements have been set up based on the measurement of the cable channel and simulation results showed these could be met with the designed circuitry. The system consists of a low-speed 16-to-1 serializing structure, a high-speed 4-to-1 Multiplexer, and a 6-bit (4b binary, 2b unary) CML DAC. The design is finished and taped out in 40-nm technology, however the chip is still in fabrication, so the results are based on simulation data only, in future research measurements will verify the working of the chip.