Energy Harvesting PMIC Design for an Extended Power-Range
Meekes, Bauke (TU Delft Electrical Engineering, Mathematics and Computer Science)
Serdijn, W.A. (mentor)
Degree granting institution
Xu, Weichen (mentor)
Du, S. (graduation committee)
Delft University of Technology
This work proposes an energy harvesting DC-DC converter that is able to efficiently process a wide input power range from 25 mW up to 250 mW, to charge a storage device used in Internet-of-Things (IoT) applications. An interleaved boost-converter topology with two inductors is used to divide the high currents over the two branches, in order to reduce the conduction losses in the MOSFET power switches at high input power.
A Maximum Power Point Tracking (MPPT) strategy is employed to find the optimal matching between the harvesting sensor, which in this case is a solar cell, and the input of the converter. The Maximum Power Point (MPP) is found by measuring the output current of the converter, decreasing the duty cycle of the switching power MOSFETs, and again measuring the output current to check if it increases. This process is repeated until the output current no longer increases, which is where the MPP will be. The duty-cycle pulses that control the power switches are generated by comparing a reference voltage representing the duty cycle with two sawtooth waves with a phase difference of 180 degrees generated on-chip.
Usually, for converters that handle large currents, large power switches are required to keep the on-resistance of the switches minimal such that the conduction losses do not dominate. Since the converter also needs to be able to efficiently convert smaller powers, the size of the power switches is made configurable. This is necessary since otherwise the gate-charge losses will become dominant. The total size of the segmented power switches are controlled digitally by a logic unit that calculates the expected input current using 2-bit representations of the measured output current and the two most significant bits of the 5-bit representation for the duty cycle set by the MPPT.
Schematic simulation results show a conversion efficiency of up to 92%. The proposed system is designed and simulated using 180 nm TSMC CMOS technology. The chip covers a total silicon area of 2.20 mm2, with an active area of 1.12 mm2.
To reference this document use:
Interleaved Boost Converter
Maximum Power Point Tracking
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© 2022 Bauke Meekes