On-chip output stage design for a continuous class-F power amplifier

Conference paper (2021)

Authors

A.K. Kumaran Electronics -

M. Pashaeifar Electronics -

Marco D'Avino Catena

L.C.N. de Vreede Electronics -

S.M. Alavi Electronics -

Research Group

Electronics () (TU Delft)

DOI: https://doi.org/10.1109/ISCAS51556.2021.9401788

Common-mode analysis Continuous class F (CCF) Differential-mode analysis Harmonic termination Output matching network Power amplifier (PA)

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Published Date

2021

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2^nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2^nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach.

Files

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- Embargo expired in 09-01-2022