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Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Efficiency of Double-barrier Magnetic Tunnel Junction-based Digital eNVM Array for Neuro-Inspired Computing
Device Aware Diagnosis for Unique Defects in STT-MRAMs
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design
PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory
Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs
Special Session: STT-MRAMs: Technology, Design and Test
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
Impact of Magnetic Coupling and Density on STT-MRAM Performance
Defect and Fault Modeling Framework for STT-MRAM Testing
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