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LJ Breems
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This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nano meter-CMOS processes. The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators. Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆Σ) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth ΔΣMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency and linearity limits of ΔΣMs, aiming at a GHz sampling frequency.
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This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nano meter-CMOS processes. The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators. Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆Σ) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth ΔΣMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency and linearity limits of ΔΣMs, aiming at a GHz sampling frequency.
A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter.
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A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter.
Journal article
(2010)
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Salvatore Drago, Domine M.W. Leenaerts, Bram Nauta, Fabio Sebastiano, Kofi A.A. Makinwa, Lucien J. Breems
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Journal article
(2009)
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Salvatore Drago, Fabio Sebastiano, Lucien J. Breems, Domine M.W. Leenaerts, Kofi A.A. Makinwa, Bram Nauta
This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 ¿W with a clock generator inaccuracy of only 1%.
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This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation scheme (impulse radio), with a bandwidth of 17.7 MHz in the 2.4 GHz-ISM band and a specific medium access control (MAC) protocol, based on a duty-cycled wake-up radio and a crystal-less clock generator. It is shown that the total average power consumption is expected to be less than 100 ¿W with a clock generator inaccuracy of only 1%.