This work presents a structured, CAD-assisted design flow to realize broadband on-wafer calibration structures, validated in the prefabrication phase, and extract the intrinsic device response up to (sub)mm-waves. The strict requirements imposed by the design rule checks (DRCs) of 22 nm CMOS technology are incorporated during the design phase of the fixture by using a scripted connectable tile elements approach. The minimum dimension of a critical feature of the fixture is then identified using a newly defined metric based on the correspondence between the EM field distribution in the fixture versus a non-perturbed case of the same standard (STD) artifact. A simulation test bench environment, augmented with experimental data, is then used to add the uncertainties arising from three main error contributors: vector network analyzer (VNA) receiver noise, probe placement error, and calibration residual errors. Including these errors allows for the generation of pre-silicon numerical uncertainty bounds, which are benchmarked with experimental data using calibration quality metrics and device-level parameters. Measurement results ranging from 1 to 325 GHz are presented to demonstrate the validity of the proposed approach to establish the quality of on-wafer calibration approaches integrated in the back-end of line of Si-based technologies and to validate the compact model of CMOS devices up to (sub)mm-waves.