Cardiovascular diseases are the leading cause of death in the devel- oped world. Preventing these deaths, require long term monitoring and manual inspection of ECG signals, which is a very time consum- ing process. Consequently, a wearable system that can automatically categorize beats is essential.
Neuromorphic machines have been introduced relatively recently in the science community. The aim of these machines is to emulate the brain. Their low power design makes them an optimal choice for a low power wearable ECG classifier.
As features are crucial in any machine learning system, this thesis aims at proposing an energy efficient feature extraction algorithm for ECG arrhythmia classification using neuromorphic machines. The feature extraction algorithm proposed in this thesis consists of the merger of a low power feature detection and a feature selection algorithm. Also, different network configurations have been investigated to achieve classification using an LSM architecture. The resulting system can accurately cluster seven beat types, has an overall classification rate of 95.5%, and consumes an estimate of 803.62 nW.

The high level of realism of spiking neuron networks and their complexity require a considerable computational resources limiting the size of the realized networks. Consequently, the main challenge in building complex and biologically accurate spiking neuron network is largely set by the high computational and data transfer demands. In this thesis, I implement several efficient models of the spiking neuron with characteristics such as axon conduction delays and spike timing-dependent plasticity in a real-time data-flow learning network. With the performance analysis, the trade-offs between the biophysical accuracy and computation complexity are defined for the different models. The experimental results indicate that the proposed real-time data-flow learning network architecture allows the capacity of over 1,188 (max.6,300, depending on the model complexity) biophysically accurate neurons in a single FPGA device.