In this paper, a novel fan-out panel-level printed circuit board (PCB) embedded package technology for silicon carbide (SiC) MOSFET power module is presented to address parasitic inductances, heat dissipation, and reliability issues that are inherent with aluminum wires used in conventional packaging scheme. To withstand high temperature beyond 175 °C and high voltage over 1.2 kV and improve thermomechanical reliability of the fan-out panel-level PCB embedded SiC power module, bismaleimide-triazine (BT) laminate and prepreg with high-temperature stability, high dielectric strength, coefficient of thermal expansion (CTE) matching with SiC, and high T-g are selected as PCB embedded package materials. Then, high-temperature stabilities, dielectric breakdown strength, and thermomechanical performances of the embedded materials are characterized. The experimental results show that the PCB embedded materials can withstand high temperature beyond 200 °C and a high voltage above 1.2 kV. T-g is as high as over 260 °C, and CTE is matching with SiC. Besides, in order to provide one guideline for the high-temperature and high-pressure laminating process during the PCB embedded SiC MOSFETs packaging, cure kinetics of BT prepreg are analyzed. The results show that 1-h curing time at 280 °C curing temperature and 2-h curing time at 210 °C curing temperature can ensure the full cure of the BT prepreg.@en

SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.@en

In this work, an experimental study on the aluminum plate fin evaporator based on a compact two-phase cooling system for high heat flux electronic packages is presented. Single-chip and multi-chip wire-bonded thermal test vehicles (TTVs) were fabricated and assembled in the PCB grooves designed to emulate high heat flux sources. The issue of heat dissipation was addressed by applying the evaporator to the TTVs, respectively, to evaluate their thermal characteristics. It is found that, the evaporator system could dissipate over 380 W/cm2 for the TTV1 while maintaining its temperature at about 90 °C. As the effective heat source area and thermal design power (TDP) increased, the maximum heat flux that the system could dissipate decreased given the same chip temperature rise. Furthermore, the addition of a second evaporator and heat source following the main evaporator, increased the dissipation of the system. As a result, an increase of 48 W/cm2 in heat removal capacity was observed in our test system. Finally, the effect of the differential pressure between the condenser and the evaporator was investigated. The increase in the differential pressure could improve the heat dissipation capacity of the two-phase cooling system. The temperature of the TTV2 dropped by 19 °C when the differential pressure increased by 2.7 bar. It can be concluded that the compact two-phase cooling system is a promising solution for removing heat from high heat flux electric packages.@en

In this work, an experimental study on the aluminum plate fin evaporator based on a compact two-phase cooling system for high heat flux electronic packages is presented. Single-chip and multi-chip wire-bonded thermal test vehicles (TTVs) were fabricated and assembled in the PCB grooves designed to emulate high heat flux sources. The issue of heat dissipation was addressed by applying the evaporator to the TTVs, respectively, to evaluate their thermal characteristics. It is found that, the evaporator system could dissipate over 380 W/cm2 for the TTV1 while maintaining its temperature at about 90 °C. As the effective heat source area and thermal design power (TDP) increased, the maximum heat flux that the system could dissipate decreased given the same chip temperature rise. Furthermore, the addition of a second evaporator and heat source following the main evaporator, increased the dissipation of the system. As a result, an increase of 48 W/cm2 in heat removal capacity was observed in our test system. Finally, the effect of the differential pressure between the condenser and the evaporator was investigated. The increase in the differential pressure could improve the heat dissipation capacity of the two-phase cooling system. The temperature of the TTV2 dropped by 19 °C when the differential pressure increased by 2.7 bar. It can be concluded that the compact two-phase cooling system is a promising solution for removing heat from high heat flux electric packages.@en

In this paper, a high power-density 3D integrated synchronous buck converter with dual side cooling structure was designed and analyzed. A novel panel-level PCB embedded package technology for MOSFETs and planar LTCC inductor of the converter was proposed to address parasitic elements, heat dissipation, and reliability issues inherent with aluminum wires used in conventional wire-bonded package. The MOSFETs and LTCC inductor were embedded in the PCB, respectively, interconnected by RDL and PCB vias. Copper-clad BT laminate and BT prepreg with low CTE and high Tg were selected and characterized by TMA. Analysis showed that the selective PCB embedding materials were very ideal for MOSFETs and LTCC inductor packaging. Thermal simulation of the 3D module was performed using ANSYS ICEPAK. To improve accuracy and efficiency of the thermal simulation, equivalent thermal conductivity of a PCB via unit was extracted and equivalent model was built. Effects of PCB vias and heat spreader on the thermal performance of the 3D converter were analyzed. The study showed that PCB vias can improve the thermal performance of the 3D module with cap heat spreader. The highest junction temperature of the optimized 3D converter was limited to about 71.2 °C.@en

In this paper, a high power-density 3D integrated synchronous buck converter with dual side cooling structure was designed and analyzed. A novel panel-level PCB embedded package technology for MOSFETs and planar LTCC inductor of the converter was proposed to address parasitic elements, heat dissipation, and reliability issues inherent with aluminum wires used in conventional wire-bonded package. The MOSFETs and LTCC inductor were embedded in the PCB, respectively, interconnected by RDL and PCB vias. Copper-clad BT laminate and BT prepreg with low CTE and high Tg were selected and characterized by TMA. Analysis showed that the selective PCB embedding materials were very ideal for MOSFETs and LTCC inductor packaging. Thermal simulation of the 3D module was performed using ANSYS ICEPAK. To improve accuracy and efficiency of the thermal simulation, equivalent thermal conductivity of a PCB via unit was extracted and equivalent model was built. Effects of PCB vias and heat spreader on the thermal performance of the 3D converter were analyzed. The study showed that PCB vias can improve the thermal performance of the 3D module with cap heat spreader. The highest junction temperature of the optimized 3D converter was limited to about 71.2 °C.@en

Throughout the history of power electronics, main driving force of developments is attribute to innovations in power semiconductor technology. With continuous technical improvements in the past 30 years, Si devices, being the most widely used power semiconductor technology, are approaching physical limits e.g. breakdown field, thermal conductivity, etc. of the basic material. Performances of power converters such as efficiency, power density, etc., therefore, has entered into a stage that further improvements are not likely to happen without revolutionary advance in power semiconductor technology. GaN power semiconductor devices, judging from the wide bandgap nature of its material, have the potential of outperforming conventional Si counterparts in measures of high voltage, high temperature and high frequency operations. Capabilities of a GaN device, however, is influenced by more issues, which, apart from material properties, also include die design and fabrication approaches, device packaging technologies, how they are used in an application, etc. In fact, at this stage, available GaN transistors are mostly of lateral structure and, as a consequence, confined to low voltage ones (<1kW) while maximum junction temperature of these products is limited to 175 °C because of the lack of suitable packaging technologies. So far, high frequency operation performance of GaN power semiconductors is unknown and needs to be investigated. This thesis explores high frequency operation potentials of single-die, normally-off GaN power semiconductors that are suited for high voltage, low current applications. The exploration is carried out by means of conducting loss modeling of GaN transistors, uncovering desirable operation conditions of GaN devices for high frequency operations according to analysed results from the model, identifying optimal topologies and operation modes in power converters that can facilitate such conditions for GaN to achieve optimal utilization of the new technology and demonstrating potentials of GaN power semiconductors in an application with all the developed techniques employed.@en

In this paper, losses in a 600V Gallium Nitride (GaN) Gate Injection Transistor (GIT) were evaluated in different operation modes of a boost converter. Analytical loss model of GaN GIT, in which circuit and package parasitics are accounted for, was developed to assist the evaluation. Losses in GIT were assessed in a boost converter using the model and the results showed that: in Continuous Conduction Mode (CCM) and Boundary Conduction Mode (BCM), turn-on loss, mainly originated from discharging of transistor output capacitance, dominates in GIT; in Boundary Conduction Mode with Valley Switching (BCM-VS), where transistor is switched on with reduced voltage and zero current, turn-on loss can be greatly reduced. In BCM-VS, where turn-off current is higher than CCM and BCM, turn-off loss dominates as C,gd is large and the ratio between Cds and Cgd is small in low voltage range. Experiments were performed to validate the loss model at both 100kHz and 1MHz as well as to prove and demonstrate the loss analysis.@en

In this paper, losses in a 600V Gallium Nitride (GaN) Gate Injection Transistor (GIT) were evaluated in different operation modes of a boost converter. Analytical loss model of GaN GIT, in which circuit and package parasitics are accounted for, was developed to assist the evaluation. Losses in GIT were assessed in a boost converter using the model and the results showed that: in Continuous Conduction Mode (CCM) and Boundary Conduction Mode (BCM), turn-on loss, mainly originated from discharging of transistor output capacitance, dominates in GIT; in Boundary Conduction Mode with Valley Switching (BCM-VS), where transistor is switched on with reduced voltage and zero current, turn-on loss can be greatly reduced. In BCM-VS, where turn-off current is higher than CCM and BCM, turn-off loss dominates as C,gd is large and the ratio between Cds and Cgd is small in low voltage range. Experiments were performed to validate the loss model at both 100kHz and 1MHz as well as to prove and demonstrate the loss analysis.@en