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Journal article(2026)
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L.Z. Endrinal, Jehan Saujauddin, Yuan Chung Ho, Dilbagh Singh, Sasi Sekaran Sundaresan, Vinod Kumar Kakumanu, Jessen Gonzalez, Willem D. van Driel, G. Q. Zhang
The rapid growth of generative Artificial Intelligence (AI), automotive electrification and Internet of Things (IoT) is driving an unprecedented demand for high-performance Integrated Circuits (ICs), projected to push the semiconductor industry to a $1 trillion business by 2030 (Burkacky et al., 2022; PWC, 2025). This drove the adoption of advanced process (FinFET, Gate-All-Around, Forksheet, CFET, Backside Power Delivery Network) and 3D package technologies (chiplets, Heterogeneous Integration, Co-packaged Optics). Unfortunately, component stacking in 3D ICs such as Package-on-Package (PoP) products creates an optical barrier during Electrical Fault Isolation (EFI). This paper presents a novel Failure Analysis (FA) hardware and sample preparation solution that enables System-Level FA on mobile System-on-a-Chip (SoC) PoP devices, where the DRAM is stacked atop the logic controller device. The primary challenge in performing EFI on the bottom die is providing direct line-of-sight (LoS) access while preserving the top DRAM functionality through extremely small interconnects called Through Interposer Vias (TIVs). For the first time, this groundbreaking hardware solution overcomes the challenge of connecting a DRAM atop the SoC silicon, utilizing the smallest possible interposer pin pitch (∼210 um) and advanced DRAM card design that incorporates stringent design rules to enable up to 6.3 Gbps using a DDR training test and runs standard Android stress applications. The results of the FA hardware solution for SLT platform will be discussed, together with several FA use cases that were enabled through this innovative solution. Lastly, this paper will discuss the limitations of this hardware, together with opportunities for improvement and further work. This novel solution paves the way for the failure analysis of 3D IC devices on a system level platform, which are utilized not only in mobile applications, but also for cloud, server, and quantum computing ICs assembled in complex packages.
...
The rapid growth of generative Artificial Intelligence (AI), automotive electrification and Internet of Things (IoT) is driving an unprecedented demand for high-performance Integrated Circuits (ICs), projected to push the semiconductor industry to a $1 trillion business by 2030 (Burkacky et al., 2022; PWC, 2025). This drove the adoption of advanced process (FinFET, Gate-All-Around, Forksheet, CFET, Backside Power Delivery Network) and 3D package technologies (chiplets, Heterogeneous Integration, Co-packaged Optics). Unfortunately, component stacking in 3D ICs such as Package-on-Package (PoP) products creates an optical barrier during Electrical Fault Isolation (EFI). This paper presents a novel Failure Analysis (FA) hardware and sample preparation solution that enables System-Level FA on mobile System-on-a-Chip (SoC) PoP devices, where the DRAM is stacked atop the logic controller device. The primary challenge in performing EFI on the bottom die is providing direct line-of-sight (LoS) access while preserving the top DRAM functionality through extremely small interconnects called Through Interposer Vias (TIVs). For the first time, this groundbreaking hardware solution overcomes the challenge of connecting a DRAM atop the SoC silicon, utilizing the smallest possible interposer pin pitch (∼210 um) and advanced DRAM card design that incorporates stringent design rules to enable up to 6.3 Gbps using a DDR training test and runs standard Android stress applications. The results of the FA hardware solution for SLT platform will be discussed, together with several FA use cases that were enabled through this innovative solution. Lastly, this paper will discuss the limitations of this hardware, together with opportunities for improvement and further work. This novel solution paves the way for the failure analysis of 3D IC devices on a system level platform, which are utilized not only in mobile applications, but also for cloud, server, and quantum computing ICs assembled in complex packages.
The relentless pursuit of high-performance computing driven by 5G/6G, artificial intelligence, autonomous driving, Internet of things (IoT), quantum computing, and data centers has pushed traditional integrated circuit scaling to its limits [1]. As lithography challenges and escalating manufacturing costs slow Moore’s law, the industry has pivoted toward design technology co-optimization (DTCO) and system technology co-optimization (STCO). These methodologies extend device performance through process and package scaling, introducing complex transistor architectures like gate-all-around (GAA), forksheets, and complementary FETs (CFET), alongside system-level innovations like backside power deliver networks (BPDN), 3D IC, and heterogeneous integration. While these advancements optimize power, performance, area, and cost (PPAC), they inadvertently create a significant bottleneck in failure analysis (FA). Advanced package technologies such as co-packaged optics, heterogeneous integration, and chiplets have fundamentally disrupted electrical fault isolation (EFI) flows. Complex package routing and dense 3D stacking of multiple components now pose severe challenges to fault isolation. Historically, the industry relied on design for test (DFT) to screen defects and design for diagnosis (DFD) to predict failure locations. However, in advanced nodes, diagnostic quality is often insufficient to characterize underlying failure mechanisms, and design complexity restricts accessibility and controllability of internal signals needed for EFI. This paper reviews the impact of DTCO and STCO on failure analysis, identifying key challenges and drivers. FA has traditionally been treated as a post-silicon afterthought; chip and hardware designs rarely consider its workflows. Yet, as new technologies evolve, FA becomes a critical bottleneck to yield learning, slowing down yield ramp-up and time-to-market. This paper calls for a strategic “left-shift” of FA requirements early into the design cycle through design for analysis (DFA). By integrating dedicated DFA features, manufacturers can bridge the gap between silicon design and post-silicon debug, transforming FA into a proactive driver of yield.
...
The relentless pursuit of high-performance computing driven by 5G/6G, artificial intelligence, autonomous driving, Internet of things (IoT), quantum computing, and data centers has pushed traditional integrated circuit scaling to its limits [1]. As lithography challenges and escalating manufacturing costs slow Moore’s law, the industry has pivoted toward design technology co-optimization (DTCO) and system technology co-optimization (STCO). These methodologies extend device performance through process and package scaling, introducing complex transistor architectures like gate-all-around (GAA), forksheets, and complementary FETs (CFET), alongside system-level innovations like backside power deliver networks (BPDN), 3D IC, and heterogeneous integration. While these advancements optimize power, performance, area, and cost (PPAC), they inadvertently create a significant bottleneck in failure analysis (FA). Advanced package technologies such as co-packaged optics, heterogeneous integration, and chiplets have fundamentally disrupted electrical fault isolation (EFI) flows. Complex package routing and dense 3D stacking of multiple components now pose severe challenges to fault isolation. Historically, the industry relied on design for test (DFT) to screen defects and design for diagnosis (DFD) to predict failure locations. However, in advanced nodes, diagnostic quality is often insufficient to characterize underlying failure mechanisms, and design complexity restricts accessibility and controllability of internal signals needed for EFI. This paper reviews the impact of DTCO and STCO on failure analysis, identifying key challenges and drivers. FA has traditionally been treated as a post-silicon afterthought; chip and hardware designs rarely consider its workflows. Yet, as new technologies evolve, FA becomes a critical bottleneck to yield learning, slowing down yield ramp-up and time-to-market. This paper calls for a strategic “left-shift” of FA requirements early into the design cycle through design for analysis (DFA). By integrating dedicated DFA features, manufacturers can bridge the gap between silicon design and post-silicon debug, transforming FA into a proactive driver of yield.
