Objective. Ensuring the longevity of implantable devices is critical for their clinical usefulness. This is commonly achieved by hermetically sealing the sensitive electronics in a water impermeable housing, however, this method limits miniaturisation. Alternatively, silicone encapsulation has demonstrated long-term protection of implanted thick-film electronic devices. However, much of the current conformal packaging research is focused on more rigid coatings, such as parylene, liquid crystal polymers and novel inorganic layers. Here, we consider the potential of silicone to protect implants using thin-film technology with features 33 times smaller than thick-film counterparts. Approach. Aluminium interdigitated comb structures under plasma-enhanced chemical vapour deposited passivation (SiO x , SiO x N y , SiO x N y + SiC) were encapsulated in medical grade silicones, with a total of six passivation/silicone combinations. Samples were aged in phosphate-buffered saline at 67 °C for up to 694 days under a continuous 5 V biphasic waveform. Periodic electrochemical impedance spectroscopy measurements monitored for leakage currents and degradation of the metal traces. Fourier-transform infrared spectroscopy, x-ray photoelectron spectroscopy, focused-ion-beam and scanning-electron- microscopy were employed to determine any encapsulation material changes. Main results. No silicone delamination, passivation dissolution, or metal corrosion was observed during ageing. Impedances greater than 100 GΩ were maintained between the aluminium tracks for silicone encapsulation over SiO x N y and SiC passivations. For these samples the only observed failure mode was open-circuit wire bonds. In contrast, progressive hydration of the SiO x caused its resistance to decrease by an order of magnitude. Significance. These results demonstrate silicone encapsulation offers excellent protection to thin-film conducting tracks when combined with appropriate inorganic thin films. This conclusion corresponds to previous reliability studies of silicone encapsulation in aqueous environments, but with a larger sample size. Therefore, we believe silicone encapsulation to be a realistic means of providing long-term protection for the circuits of implanted electronic medical devices.@en

A fully implantable multi-channel neural prosthesis for epidural stimulation will be demonstrated. The prosthesis features three telemetry-operated independent stimulators providing in total eighteen stimulation channels. The stimulator circuits were implemented in a 0.6-μm CMOS technology. The prosthesis is protected in a hermetically sealed ceramic enclosure and encapsulated in medical grade silicone rubber for long-term implantation. During the live demonstration in-vitro tests with electrodes in saline will be performed with the prosthesis operated wirelessly from a remote computer.@en

A fully implantable multi-channel neural prosthesis for epidural stimulation will be demonstrated. The prosthesis features three telemetry-operated independent stimulators providing in total eighteen stimulation channels. The stimulator circuits were implemented in a 0.6-μm CMOS technology. The prosthesis is protected in a hermetically sealed ceramic enclosure and encapsulated in medical grade silicone rubber for long-term implantation. During the live demonstration in-vitro tests with electrodes in saline will be performed with the prosthesis operated wirelessly from a remote computer.@en

This paper presents a second-generation integrated circuit for the Active Books neural stimulation microsystem. It provides multi-channel stimulation with versatile control of stimulation profiles and reduced crosstalk from other stimulation channels. The new design features enhanced safety by monitoring the temperature and humidity inside the micropackage, and the peak electrode voltage at any stimulating electrode. The humidity sensor uses an interdigitated capacitor covered by a passivation layer and a polyimide covering. To boost sensitivity in the operating range of interest, the temperature sensor uses a temperature-insensitive current that is subtracted from a proportional-to-absolute-temperature current. A 3-b analog-to-digital converter is used to record the peak electrode voltage. All sensor data is sent to an implanted central hub using bidirectional connection with error checking. Both the stimulation electronics and sensors are integrated on a 6.2 mm 4 mm silicon die using XFAB's 0.6- μ m CMOS high-voltage process. No post-processing steps are involved. The stimulator uses a five-wire cable to provide the power supply and bidirectional data signals. The chip operates from a 7.5-18 V power supply and can generate stimulation currents of 1 mA, 4 mA or 8 mA with a pulse duration of 2 μ S-1.07 ms. The humidity sensor output varies linearly with relative humidity (RH) with a normalized sensitivity of 0.04%/%RH over the range of 20-90%RH. The temperature sensor has a nonlinearity of 0.4% over the range of 20-90 °C and a resolution of 0.12 °C. The stimulator is the first of its kind to include integrated temperature and humidity sensors.@en

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 μA.@en

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 μA.@en

The design of a very small low-power IC driving 16 electrodes in any combination, for testing different epidural stimulation patterns in freely moving rats using a two wire interface is presented. A scheme is proposed, to receive power, data, clocking information and stimulus current pulses from an external source via the two wires. This is achieved by a combination of time multiplexing and pulse width modulation. The architecture of the system is discussed and simulated results of some building blocks are presented.@en

The design of a very small low-power IC driving 16 electrodes in any combination, for testing different epidural stimulation patterns in freely moving rats using a two wire interface is presented. A scheme is proposed, to receive power, data, clocking information and stimulus current pulses from an external source via the two wires. This is achieved by a combination of time multiplexing and pulse width modulation. The architecture of the system is discussed and simulated results of some building blocks are presented.@en

The design of a very small low-power IC driving 16 electrodes in any combination, for testing different epidural stimulation patterns in freely moving rats using a two wire interface is presented. A scheme is proposed, to receive power, data, clocking information and stimulus current pulses from an external source via the two wires. This is achieved by a combination of time multiplexing and pulse width modulation. The architecture of the system is discussed and simulated results of some building blocks are presented.@en

We are developing an active implant for epidural spinal cord stimulation. A thin application specific integrated circuit (ASIC) (~80 μm) is to be embedded within it. The laser patterned tracks are electrically and mechanically thermosonically bonded on the ASIC pads using gold ball studs, forming micro-rivets through holes in the foil of the tracks, an interconnection method called electrical rivet bonding, or microflex [1]. In this work, we sought to characterize and optimize the technique, with respect to its bonding strength. The technique is relatively new and, so far, the mechanical strength of the bonds has only been investigated for interconnection on gold tracks. Standard ASICs however, normally come with aluminium pads. We ran a series of pull tests on the bonds between the metal tracks and aluminium ASIC pads. In these tests, we were concerned with the effect of the different parameters on the bond strength, and more specifically the size of the gold balls and the size of the holes in the foil. We recorded the maximum force (stress) before bond failure for different combinations of parameters. Our results indicate that average stress values can vary between 9.6 and 60 cN, depending on the process parameters. Different failure mechanisms have been identified and these are discussed. Overall, we conclude that larger holes provide larger contact areas with the substrate and generally result in stronger bonds, but the right combination of ball and hole sizes, could lead to strong bonds even with smaller holes.@en

Powering of medical implants by inductive coupling is an effective technique, which avoids the use of bulky implanted batteries or transcutaneous wires. On the external unit side, class-D and class-E power amplifiers (PAs) are conventionally used, thanks to their high efficiency at high frequencies. The initial specifications driving this study require the use of multiple independent stimulators, which imposes serious constraints on the area and functionality of the external unit. An integrated circuit class-D PA has been designed to provide both small area and enhanced functionality, the latter achieved by the addition of an on-chip (PLL) a dead-time generator and a phase detector. The PA was designed in a 0.18-μm CMOS high-voltage process technology and occupies an area of 9.86 mm2. It works at frequencies up to 14 MHz and 30-V supply and efficiencies higher than 80% are obtained at 14 MHz. The PA is intended for a closed-loop transmitter system that optimizes power delivery to medical implants.@en

Powering of medical implants by inductive coupling is an effective technique, which avoids the use of bulky implanted batteries or transcutaneous wires. On the external unit side, class-D and class-E power amplifiers (PAs) are conventionally used, thanks to their high efficiency at high frequencies. The initial specifications driving this study require the use of multiple independent stimulators, which imposes serious constraints on the area and functionality of the external unit. An integrated circuit class-D PA has been designed to provide both small area and enhanced functionality, the latter achieved by the addition of an on-chip (PLL) a dead-time generator and a phase detector. The PA was designed in a 0.18-μm CMOS high-voltage process technology and occupies an area of 9.86 mm2. It works at frequencies up to 14 MHz and 30-V supply and efficiencies higher than 80% are obtained at 14 MHz. The PA is intended for a closed-loop transmitter system that optimizes power delivery to medical implants.@en

This paper presents a fully implantable multi-channel neural prosthesis for epidural stimulation. The prosthesis features three telemetry-operated independent stimulators providing in total eighteen stimulation channels. The stimulator circuits were implemented in a 0.6-μm CMOS technology. The prosthesis is protected in a hermetically sealed ceramic enclosure and encapsulated in medical grade silicone rubber. In-vitro measured results with electrodes in saline are presented.@en

The efficiency of an inductive power transfer link is greatly affected by misalignment between the coils, caused by the patient's movement, after implantation. In this paper we present the preliminary design of a coupling-insensitive system with an integrated class-D transmitter, suitable for powering epidural stimulation implants. The operation of the system is based on closed-loop modulation of the power delivered to the implant, to compensate for losses of coupling between coils after implantation. An integrated transmitter with efficiencies above 90% was designed to operate between 1 MHz and 14 MHz. The circuit design employs 0.18-um high-voltage CMOS technology. Simulations are presented to verify the operation of the circuit.@en

This paper presents a modified 1-Wire® based communication architecture between one active and several passive units of a distributed implantable system. The passive slave units are embedded in the electrode array. We focus in particular on the introduction of the physical and data link layer of the communication block, and present post-layout results of simulated data transfer between the hub and one slave in 0.18-μm power management CMOS technology. The communication block has a power consumption of 12.5 μW for a gross bit rate of 11.1 kBit/s. The proposed interface is inherently safe and suitable for exchanging status and sensor data between implants. The possibility to achieve higher symbol rates is discussed.@en

This paper discusses the design of an application-specific integrated circuit (ASIC) suitable for mounting on a multi-electrode array for epidural spinal cord stimulation in rats. The ASIC acts as a demultiplexer, driving 12 electrodes on the array in any configuration. It is capable of routing biphasic constant current pulses of up to 1 mA to high impedance loads (with a maximum output voltage swing of approximately 25 V) and is small enough to be implanted into a rat's spinal column. Communication with its driver is achieved via 3 wires to minimize the number of interconnections. The circuit was implemented in a 0.18-μm high-voltage CMOS technology occupying a core area of 0.36 mm 2. Power dissipation is about 110 μW. Post-layout simulations are presented which show the correct operation of the system.@en

This paper discusses the design of an application-specific integrated circuit (ASIC) suitable for mounting on a multi-electrode array for epidural spinal cord stimulation in rats. The ASIC acts as a demultiplexer, driving 12 electrodes on the array in any configuration. It is capable of routing biphasic constant current pulses of up to 1 mA to high impedance loads (with a maximum output voltage swing of approximately 25 V) and is small enough to be implanted into a rat's spinal column. Communication with its driver is achieved via 3 wires to minimize the number of interconnections. The circuit was implemented in a 0.18-μm high-voltage CMOS technology occupying a core area of 0.36 mm 2. Power dissipation is about 110 μW. Post-layout simulations are presented which show the correct operation of the system.@en

We are developing an electrode array for epidural spinal cord stimulation and a thin integrated circuit (IC) is to be embedded in it. This paper focuses on the development and characterization of a manual process for thinning individual IC die and discusses the issues associated with thinning small dice by a manual process. The procedure allows easy and controlled post-separation thinning of small (about 1 mm2) silicon chips by grinding. A systematic approach was followed to characterize the technique and repeatability of the results. With the setup we introduced we were able to control the final thickness of the IC with a standard deviation of 9.2 μm. Although no chemical processing is used, a small grit size film can create smooth surfaces, with roughness comparable to reported values after etching, acting as the so-called 'stress-relief' step. Electrical tests performed on a thinned stimulator output stage IC indicated that no die damage was caused by the procedure. Some issues regarding the integration of thinned ICs on flexible substrates and the reliability of gold ball rivet bonds on the ICs' aluminium pads are also discussed.@en