BJ

B.H.H. Juurlink

112 records found

Scalable parallel programming applied to H.264/AVC decoding

A predictor-based power-saving policy for DRAM memories

Nexus: hardware support for task-based programming

Composable Local Memory Organisation for Streaming Applications on Embedded MPSoCs

An Instruction to Accelerate Software Caches

A case for hardware task management support for the StarSS programming

Evaluation of parallel H.264 decoding strategies for the cell broadband engine

Instruction precomputation with memoization for fault detection

A multidimensional software cache for scratchpad-based systems

The SARC architecture

Extending the cell SPE with energy efficient branch prediction

Protective redundancy overhead reduction using instruction vulnerability factor

Instruction precomputation for fault detection

Scalar processing overhead on SIMD-only architectures

Energy efficient branch prediction on the cell SPE

Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture

Performance improvement of multimedia kernels by alleviating overhead instructions on SIMD devices

Specialization of the cell SPE for media applications

Parallel H.264 decoding on an embedded multicore processor

Limiting the number of dirty cache lines
Conference paper (2009) - PJ de Langen (author), B Juurlink (author)