Memristor-based Computation-in-Memory is one of the emerging architectures proposed to deal with Big Data problems. The design of such architectures requires a radically new automatic design flow because the memristor is a passive device that uses resistance to encode its logic value. This paper proposes a design flow for mapping parallel algorithms on the CIM architecture. Algorithms with similar data flow graphs can be mapped on the crossbar using the same template containing scheduling, placement, and routing information; this template is named skeleton. By configuring such a skeleton with different pre-designed circuits, we can build CIM implementations of the corresponding algorithms in that class. This approach does not only map an algorithm on a memristor crossbar, but also gives an estimation of its performance, area, and energy consumption. It also supports user-defined constraints and parallel SystemC simulation. Experimental results demonstrate the feasibility and the potential of the approach.@en

One of the most critical challenges for today's and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.@en

One of the most critical challenges for today's and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.@en

One of the most critical challenges for today's and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.@en

One of the most critical challenges for today's and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.@en

One of the most critical challenges for today's and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.@en

One of the most critical challenges for today's and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.@en

The advent and subsequent popularity of low cost, low power CMOS vision sensors enables us to integrate processing logic on the camera chip itself, thereby creating so-called smart sensors. They have an on-chip SIMD data processing array controlled by an off-chip controller. Smart sensors can execute low-level image processing routines as soon as one or more image lines are converted; they do not have to wait for the whole image. High level image processing like feature extraction and object detection and tracking can be performed with a separate powerful off-chip processor. Current solutions have several problems. It is totally unclear what the right architectural parameters are for a given application domain. There are many parameters, like pixel array size, pixel properties, number of AD-converter units, accuracy, number of pixels per SIMD processor element, processor element functionality, etc. Also the functionality of the external processor and its connectivity with the smart sensor has to be determined. Furthermore, intuitive mappings of algorithms on architecture components are used, after the architecture has been determined. It will be clear that this is far from optimal. Finally we foresee a further integration, making a combination of on-chip vision sensor, pixel processing, control, and feature / object processing possible. The result is a low-cost one-chip smart camera (so-called SmartCam) solution. This means that research is needed to explore the new architectural opportunities and consequences. The SmartCam project investigates these new opportunities and contributes to a better and more quantitatively guided design trajectory. In particular, we will investigate the impact of current applications, de¯ne relevant architectural parameters and develop an architectural template, enhance our existing application mapping environments for SIMD and ILP (Instruction-Level Parallel) processors, and perform two case studies. The work will focus on creating an environment for exploring the design space parametrized by the architectural template and integrating this with our application mapping environment. Keywords: Embedded system design, Smart Sensors, Design Space Exploration, Parametric design, Programmable design, Heterogeneous architecture, Low power, High performance, Small and Cheap implementations@en

The advent and subsequent popularity of low cost, low power CMOS vision sensors enables us to integrate processing logic on the camera chip itself, thereby creating so-called smart sensors. They have an on-chip SIMD data processing array controlled by an off-chip controller. Smart sensors can execute low-level image processing routines as soon as one or more image lines are converted; they do not have to wait for the whole image. High level image processing like feature extraction and object detection and tracking can be performed with a separate powerful off-chip processor. Current solutions have several problems. It is totally unclear what the right architectural parameters are for a given application domain. There are many parameters, like pixel array size, pixel properties, number of AD-converter units, accuracy, number of pixels per SIMD processor element, processor element functionality, etc. Also the functionality of the external processor and its connectivity with the smart sensor has to be determined. Furthermore, intuitive mappings of algorithms on architecture components are used, after the architecture has been determined. It will be clear that this is far from optimal. Finally we foresee a further integration, making a combination of on-chip vision sensor, pixel processing, control, and feature / object processing possible. The result is a low-cost one-chip smart camera (so-called SmartCam) solution. This means that research is needed to explore the new architectural opportunities and consequences. The SmartCam project investigates these new opportunities and contributes to a better and more quantitatively guided design trajectory. In particular, we will investigate the impact of current applications, de¯ne relevant architectural parameters and develop an architectural template, enhance our existing application mapping environments for SIMD and ILP (Instruction-Level Parallel) processors, and perform two case studies. The work will focus on creating an environment for exploring the design space parametrized by the architectural template and integrating this with our application mapping environment. Keywords: Embedded system design, Smart Sensors, Design Space Exploration, Parametric design, Programmable design, Heterogeneous architecture, Low power, High performance, Small and Cheap implementations@en

The advent and subsequent popularity of low cost, low power CMOS vision sensors enables us to integrate processing logic on the camera chip itself, thereby creating so-called smart sensors. They have an on-chip SIMD data processing array controlled by an off-chip controller. Smart sensors can execute low-level image processing routines as soon as one or more image lines are converted; they do not have to wait for the whole image. High level image processing like feature extraction and object detection and tracking can be performed with a separate powerful off-chip processor. Current solutions have several problems. It is totally unclear what the right architectural parameters are for a given application domain. There are many parameters, like pixel array size, pixel properties, number of AD-converter units, accuracy, number of pixels per SIMD processor element, processor element functionality, etc. Also the functionality of the external processor and its connectivity with the smart sensor has to be determined. Furthermore, intuitive mappings of algorithms on architecture components are used, after the architecture has been determined. It will be clear that this is far from optimal. Finally we foresee a further integration, making a combination of on-chip vision sensor, pixel processing, control, and feature / object processing possible. The result is a low-cost one-chip smart camera (so-called SmartCam) solution. This means that research is needed to explore the new architectural opportunities and consequences. The SmartCam project investigates these new opportunities and contributes to a better and more quantitatively guided design trajectory. In particular, we will investigate the impact of current applications, de¯ne relevant architectural parameters and develop an architectural template, enhance our existing application mapping environments for SIMD and ILP (Instruction-Level Parallel) processors, and perform two case studies. The work will focus on creating an environment for exploring the design space parametrized by the architectural template and integrating this with our application mapping environment. Keywords: Embedded system design, Smart Sensors, Design Space Exploration, Parametric design, Programmable design, Heterogeneous architecture, Low power, High performance, Small and Cheap implementations@en