13 records found
1
An improved RNS reverse converter for the {2 2n+1-1, 2n, 2n-1} moduli set
Residue-to-binary converters for the moduli set {2 2n+1, 2 2n, 2n-1}
Low power microarchitecture with instruction reuse
Merged computation for whirlpool hashing
On-the-fly attestation of reconfigurable hardware
BRAM-LUT tradeoff on a polymorphic DES design
Cost-efficient SHA hardware accelerators
Dynamic FPGA reconfigurations with run-time region delimitation
Reconfigurable cryptographic processor
Reconfigurable memory based AES co-processor
Improving SHA-2 hardware implementations
Rescheduling for optimized SHA-1 calculation
Polymorphic AES encryption implementation
