KW
K. Wu
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1
In additive manufacturing, the fabrication sequence has a large influence on the quality of manufactured components. While planning of the fabrication sequence is typically performed after the component has been designed, recent developments have demonstrated the possibility and benefits of simultaneous optimization of both the structural layout and the corresponding fabrication sequence. This is particularly relevant in multi-axis additive manufacturing, where rotational motion offers enhanced flexibility compared to planar fabrication. The simultaneous optimization approach, called space–time topology optimization, introduces a pseudo-time field to encode the manufacturing process order, alongside a pseudo-density field representing the structural layout. To comply with manufacturing principles, the pseudo-time field needs to be monotonic, i.e., free of local minima. However, explicitly formulated constraints proposed in prior work are not always effective, particularly for complex structural layouts that commonly result from topology optimization. In this paper, we introduce a novel method to regularize the pseudo-time field in space–time topology optimization. We conceptualize the monotonic additive manufacturing process as a virtual heat conduction process starting from the surface upon which a component is constructed layer by layer. The virtual temperature field, which shall not be confused with the actual temperature field during manufacturing, serves as an analogy for encoding the fabrication sequence. In this new formulation, we use local virtual heat conductivity coefficients as optimization variables to steer the temperature field and, consequently, the fabrication sequence. The virtual temperature field is inherently free of local minima due to the physics it resembles. We numerically validate the effectiveness of this regularization in space–time topology optimization under process-dependent loads, including gravity and thermomechanical loads.
...
In additive manufacturing, the fabrication sequence has a large influence on the quality of manufactured components. While planning of the fabrication sequence is typically performed after the component has been designed, recent developments have demonstrated the possibility and benefits of simultaneous optimization of both the structural layout and the corresponding fabrication sequence. This is particularly relevant in multi-axis additive manufacturing, where rotational motion offers enhanced flexibility compared to planar fabrication. The simultaneous optimization approach, called space–time topology optimization, introduces a pseudo-time field to encode the manufacturing process order, alongside a pseudo-density field representing the structural layout. To comply with manufacturing principles, the pseudo-time field needs to be monotonic, i.e., free of local minima. However, explicitly formulated constraints proposed in prior work are not always effective, particularly for complex structural layouts that commonly result from topology optimization. In this paper, we introduce a novel method to regularize the pseudo-time field in space–time topology optimization. We conceptualize the monotonic additive manufacturing process as a virtual heat conduction process starting from the surface upon which a component is constructed layer by layer. The virtual temperature field, which shall not be confused with the actual temperature field during manufacturing, serves as an analogy for encoding the fabrication sequence. In this new formulation, we use local virtual heat conductivity coefficients as optimization variables to steer the temperature field and, consequently, the fabrication sequence. The virtual temperature field is inherently free of local minima due to the physics it resembles. We numerically validate the effectiveness of this regularization in space–time topology optimization under process-dependent loads, including gravity and thermomechanical loads.
Recent decades have seen impressive developments in the field of integrated
photonics. Chips with complex photonic functionality can presently be designed
and fabricated. Photonic packages consist of one or more PICs, as well as other
(micro-optical) components, and a fibre (array) to establish the external optical
interface. A core challenge is the assembly and packaging of these complex
devices, involving sub-μm alignment of components. To overcome the
limitations in multi-chip photonic packaging, a concept is proposed which uses
on-chip actuators for the fine-alignment of flexible waveguide structures.
...
Recent decades have seen impressive developments in the field of integrated
photonics. Chips with complex photonic functionality can presently be designed
and fabricated. Photonic packages consist of one or more PICs, as well as other
(micro-optical) components, and a fibre (array) to establish the external optical
interface. A core challenge is the assembly and packaging of these complex
devices, involving sub-μm alignment of components. To overcome the
limitations in multi-chip photonic packaging, a concept is proposed which uses
on-chip actuators for the fine-alignment of flexible waveguide structures.
Photonic packaging, which includes high-precision assembly of photonic sub-systems, is currently a bottleneck in the development of commercially-available integrated photonic products. In the pursuit of a fully-automated, high-precision, and cost-effective photonic alignment scheme for two multi-channel photonic chips, this paper explores different designs of the on-chip electrothermal actuators for positioning mechanically-flexible waveguide structures. The final alignment goal is ~100nm waveguide to waveguide. The on-chip actuators, particularly for out-of-plane actuation, are built in a 16μm-thick SiO2 photonic-material stack with 5μm-thick poly-Si as an electrothermal element. A major challenge of out-of-plane positioning is a 6μm height difference of the waveguides to be aligned, due to different built-up material stacks, together with a misalignment tolerance of 1 μm-2μm from the pre-assembly (flip-chip) process. Therefore, the bimorph-actuator design needs to compensate this height difference, and provide sufficient motion to align the waveguides. We propose to exploit the post-release deformation of so-called short-loop bimorph actuator designs to meet these joint demands. We explore different design variants based on the heater location and the integration of actuator beams with waveguide beams. The actuator design (with 30μm poly-Si and 900μm SiO2 in length) has ~8μm out-of-plane deflection and is able to generate ~4μm motion, which meets the design goal.
...
Photonic packaging, which includes high-precision assembly of photonic sub-systems, is currently a bottleneck in the development of commercially-available integrated photonic products. In the pursuit of a fully-automated, high-precision, and cost-effective photonic alignment scheme for two multi-channel photonic chips, this paper explores different designs of the on-chip electrothermal actuators for positioning mechanically-flexible waveguide structures. The final alignment goal is ~100nm waveguide to waveguide. The on-chip actuators, particularly for out-of-plane actuation, are built in a 16μm-thick SiO2 photonic-material stack with 5μm-thick poly-Si as an electrothermal element. A major challenge of out-of-plane positioning is a 6μm height difference of the waveguides to be aligned, due to different built-up material stacks, together with a misalignment tolerance of 1 μm-2μm from the pre-assembly (flip-chip) process. Therefore, the bimorph-actuator design needs to compensate this height difference, and provide sufficient motion to align the waveguides. We propose to exploit the post-release deformation of so-called short-loop bimorph actuator designs to meet these joint demands. We explore different design variants based on the heater location and the integration of actuator beams with waveguide beams. The actuator design (with 30μm poly-Si and 900μm SiO2 in length) has ~8μm out-of-plane deflection and is able to generate ~4μm motion, which meets the design goal.
Conference paper
(2016)
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Kerstin Wörhoff, Albert Prak, J. Balcells-Ventura, P. Uhlig, M. Seyfried, D. Rose, Raquel Santos, X. J.M. Leijtens, B. Flintham, M. Wale, D. Robbins, F. Postma, A Leinse, Kai Wu, T. J. Peters, M. Tichem, B. Amaning-Appiah, V. Renukappa, G. Vollrath
Fully automated, high precision, cost-effective assembly technology for photonic packages remains one of the main challenges in photonic component manufacturing. Next to the cost aspect the most demanding assembly task for multiport photonic integrated circuits (PICs) is the high-precision (±0.1 μm) alignment and fixing required for optical I/O in InP PICs, even with waveguide spot size conversion. In a European research initiative - PHASTFlex - we develop and investigate an innovative, novel assembly concept, in which the waveguides in a matching TriPleX interposer PIC are released during fabrication to make them movable. After assembly of both chips by flip-chip bonding on a common carrier, TriPleX based actuators and clamping functions position and fix the flexible waveguides with the required accuracy.
...
Fully automated, high precision, cost-effective assembly technology for photonic packages remains one of the main challenges in photonic component manufacturing. Next to the cost aspect the most demanding assembly task for multiport photonic integrated circuits (PICs) is the high-precision (±0.1 μm) alignment and fixing required for optical I/O in InP PICs, even with waveguide spot size conversion. In a European research initiative - PHASTFlex - we develop and investigate an innovative, novel assembly concept, in which the waveguides in a matching TriPleX interposer PIC are released during fabrication to make them movable. After assembly of both chips by flip-chip bonding on a common carrier, TriPleX based actuators and clamping functions position and fix the flexible waveguides with the required accuracy.
Conference paper
(2016)
-
Kai Wu, Tjitte Jelte Peters, Marcel Tichem, Ferry Postma, Albert Prak, Kerstin Wörhoff, Arne Leinse
This paper proposes and tests a design of electro-thermal bimorph actuators for alignment of flexible photonic waveguides fabricated in 16 μm thick SiO2. The actuators are for use in a novel alignment concept for multi-port photonic integrated circuits (PICs), in which the fine alignment is taken care of by positioning of suspended, mechanically flexible waveguide beams on one or more of the PICs. The design parameters of the bimorph actuator allow to tune both the initial relative position of the waveguide end-facets, and the motion range of the actuators. Bimorph actuators have been fabricated and characterized. The maximum out-of-plane deflection of the bimorph actuator (with 720 μm-long poly-Si) can reach 18:5 μm with 126:42mW, sufficient for the proposed application.
...
This paper proposes and tests a design of electro-thermal bimorph actuators for alignment of flexible photonic waveguides fabricated in 16 μm thick SiO2. The actuators are for use in a novel alignment concept for multi-port photonic integrated circuits (PICs), in which the fine alignment is taken care of by positioning of suspended, mechanically flexible waveguide beams on one or more of the PICs. The design parameters of the bimorph actuator allow to tune both the initial relative position of the waveguide end-facets, and the motion range of the actuators. Bimorph actuators have been fabricated and characterized. The maximum out-of-plane deflection of the bimorph actuator (with 720 μm-long poly-Si) can reach 18:5 μm with 126:42mW, sufficient for the proposed application.