Architecture enhancements for the ADRES coarse-grained reconfigurable array

Low power microarchitecture with instruction reuse

Embedded Computer Systems: Architectures, Modeling, and Simulation

ADRES & DRESC: Architecture and compiler for coarse-grain reconfigurable processors

Architectural Exploration of the ADRES coarse-grained reconfigurable array

Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring

Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.2624/AVC deblocking filter

MT-adres: multithreading on coarse-grained reconfigurable architecture

Hardware and a tool chain for ADRES

A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme