10 records found
1
Low power microarchitecture with instruction reuse
Architecture enhancements for the ADRES coarse-grained reconfigurable array
Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.2624/AVC deblocking filter
Embedded Computer Systems: Architectures, Modeling, and Simulation
Architectural Exploration of the ADRES coarse-grained reconfigurable array
MT-adres: multithreading on coarse-grained reconfigurable architecture
ADRES & DRESC: Architecture and compiler for coarse-grain reconfigurable processors
A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme
Hardware and a tool chain for ADRES