HW
Huan Wu
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5 records found
1
Journal article
(2026)
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Jingping Zhang, Houcai Luo, Huan Wu, Bofeng Zheng, Guoqi Zhang, Xianping Chen
Field-Stop Insulated Gate Bipolar Transistors (FS-IGBTs) are widely used in various power applications due to their low conduction and switching losses. However, further reductions in cell pitch lead to increased cell density, resulting in higher saturation current that adversely impacts the short-circuit ruggedness essential for applications such as welding machines and motor drives. This paper details the design and fabrication of a 650V, 75A FS-IGBT. By incorporating dummy gate and emitter trench structures within the active gate and optimizing the layout of the three cell structures, the short-circuit characteristics of the device are markedly improved. Experimental tests confirm that the device exhibits both low saturation on-state voltage and short-circuit ruggedness. This study further investigates the circuit parameters related to short-circuit conditions and comprehensively analyzes the impact of each parameter on the short-circuit characteristics of the FS-IGBT. The experimental results indicate that the bus voltage VDC, gate voltage VG, and temperature TC significantly influence the short-circuit performance of the FS-IGBT. Therefore, a moderate decrease in VDC, VG, and TC can effectively enhance the short-circuit ruggedness and the short-circuit withstand time tSC of the device.
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Field-Stop Insulated Gate Bipolar Transistors (FS-IGBTs) are widely used in various power applications due to their low conduction and switching losses. However, further reductions in cell pitch lead to increased cell density, resulting in higher saturation current that adversely impacts the short-circuit ruggedness essential for applications such as welding machines and motor drives. This paper details the design and fabrication of a 650V, 75A FS-IGBT. By incorporating dummy gate and emitter trench structures within the active gate and optimizing the layout of the three cell structures, the short-circuit characteristics of the device are markedly improved. Experimental tests confirm that the device exhibits both low saturation on-state voltage and short-circuit ruggedness. This study further investigates the circuit parameters related to short-circuit conditions and comprehensively analyzes the impact of each parameter on the short-circuit characteristics of the FS-IGBT. The experimental results indicate that the bus voltage VDC, gate voltage VG, and temperature TC significantly influence the short-circuit performance of the FS-IGBT. Therefore, a moderate decrease in VDC, VG, and TC can effectively enhance the short-circuit ruggedness and the short-circuit withstand time tSC of the device.
Journal article
(2025)
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Huan Wu, Houcai Luo, Jingping Zhang, Bofeng Zheng, Ruonan Wang, G. Q. Zhang, Xianping Chen
This article compares and evaluates the single pulse short-circuit robustness of silicon carbide (SiC) MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.
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This article compares and evaluates the single pulse short-circuit robustness of silicon carbide (SiC) MOSFETs with linear and hexagonal cell topologies under different gate voltages, bus voltages, and case temperatures. The short-circuit failure mechanisms of the linear and hexagonal cell topologies are studied. A new switching model for gate failure and thermal runaway short-circuit failure modes is proposed and analyzed. The robustness performance of the linear and hexagonal cell topologies is compared and evaluated under the same short-circuit power for the first time, fully revealing the comprehensive impact mechanism of cell topologies on the short-circuit robustness for SiC MOSFETs.
Journal article
(2025)
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Hou Cai Luo, Jing Ping Zhang, Ruo nan Wang, Huan Wu, Bo Feng Zheng, Kai Zheng, Guo Qi Zhang, Xian Ping Chen
The 1.2 kV SiC VDMOSFETs with varied JFET width (LJFET) are designed and fabricated in this study. The static and dynamic characteristics of each design are measured and compared. There is the best trade-off performance in the design of LJFET = 1.8 μm according to FOM (BV2/Ron) and FOM (Ciss/Crss). Besides, the surge capacity and evaluation for series designs are investigated under conditions of Vgs = 0 V and Vgs = −5 V. There is a best surge capacity in design of LJFET=1.2 μm, and the largest surge energy is the design of LJFET=2.0 μm. Further, the surge failure mechanisms of LJFET = 1.2 μm, 1.8 μm, and 2.0 μm under condition of Vgs = −5 V are investigated by decapsulated and FIB. Besides, the TCAD simulation was employed to theoretical analysis. The results show that the extremely high temperature was generated instantaneously under surge condition, resulting in epoxy carbonization, polysilicon melting and ILD oxide crack in failed position. Besides, the surge dissipating energy causes an instantaneous high temperature on the entire chip, resulting in aluminum remetallization. This paper would provide suggestions for device design and surge study.
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The 1.2 kV SiC VDMOSFETs with varied JFET width (LJFET) are designed and fabricated in this study. The static and dynamic characteristics of each design are measured and compared. There is the best trade-off performance in the design of LJFET = 1.8 μm according to FOM (BV2/Ron) and FOM (Ciss/Crss). Besides, the surge capacity and evaluation for series designs are investigated under conditions of Vgs = 0 V and Vgs = −5 V. There is a best surge capacity in design of LJFET=1.2 μm, and the largest surge energy is the design of LJFET=2.0 μm. Further, the surge failure mechanisms of LJFET = 1.2 μm, 1.8 μm, and 2.0 μm under condition of Vgs = −5 V are investigated by decapsulated and FIB. Besides, the TCAD simulation was employed to theoretical analysis. The results show that the extremely high temperature was generated instantaneously under surge condition, resulting in epoxy carbonization, polysilicon melting and ILD oxide crack in failed position. Besides, the surge dissipating energy causes an instantaneous high temperature on the entire chip, resulting in aluminum remetallization. This paper would provide suggestions for device design and surge study.
Journal article
(2023)
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Jingping Zhang, Houcai Luo, Huan Wu, Zeping Wang, Bofeng Zheng, Guoqi Zhang, Xianping Chen
A novel 4H-SiC Multiple Stepped SGT MOSFET (MSGT-MOSFET) is presented and investigated utilizing TCAD simulations in this paper. We have quantitatively studied the characteristics of the device through simulation modeling and physical model calculations, and comparatively analyzed the performance and application prospects of this novel device. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) of the MSGT-MOSFET are significantly reduced in comparison with the double trench MOSFET (DT-MOSFET) and the conventional SGT MOSFET (CSGT-MOSFET), due to the reduction of the overlapping area of the split gate (SG) structure and drift region. Therefore, the obtained high frequency figure of merit (HF-FOM) defined as [Ron × Cgd] reduced by 23.9% compared with DT-MOSFET and CSGT-MOSFET. And the HF-FOM [Ron × Qgd] for the MSGT-MOSFET significantly decreased by 71% and 50%, respectively, compared to that of the DT-MOSFET and CSGT-MOSFET. Furthermore, the switching loss is also simulated and calculated. And the total switching loss of the proposed MSGT-MOSFET realizes 42.9% and 21.7% reduction in comparison with the DT-MOSFET and CSGT-MOSFET. The overall enhanced performances suggest that the MSGT-MOSFET is an excellent choice for high frequency power electronic applications.
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A novel 4H-SiC Multiple Stepped SGT MOSFET (MSGT-MOSFET) is presented and investigated utilizing TCAD simulations in this paper. We have quantitatively studied the characteristics of the device through simulation modeling and physical model calculations, and comparatively analyzed the performance and application prospects of this novel device. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) of the MSGT-MOSFET are significantly reduced in comparison with the double trench MOSFET (DT-MOSFET) and the conventional SGT MOSFET (CSGT-MOSFET), due to the reduction of the overlapping area of the split gate (SG) structure and drift region. Therefore, the obtained high frequency figure of merit (HF-FOM) defined as [Ron × Cgd] reduced by 23.9% compared with DT-MOSFET and CSGT-MOSFET. And the HF-FOM [Ron × Qgd] for the MSGT-MOSFET significantly decreased by 71% and 50%, respectively, compared to that of the DT-MOSFET and CSGT-MOSFET. Furthermore, the switching loss is also simulated and calculated. And the total switching loss of the proposed MSGT-MOSFET realizes 42.9% and 21.7% reduction in comparison with the DT-MOSFET and CSGT-MOSFET. The overall enhanced performances suggest that the MSGT-MOSFET is an excellent choice for high frequency power electronic applications.
Journal article
(2023)
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Huan Wu, Houcai Luo, Jingping Zhang, Bofeng Zheng, Lei Lang, Zeping Wang, Guoqi Zhang, Xianping Chen
To investigate the unclamped inductive switch (UIS) characteristics, 1200 V silicon carbide (SiC) planar MOSFETs with four cell topologies of linear, current sharing linear, square, and hexagon are designed and manufactured. The experimental platform was built and tested. The results show that the single pulse avalanche energy density of the linear cell topology is 1.69 times higher than that of the square and 1.49 times that of the hexagon. Further, the UIS process is simulated by using physical simulation, which shows that the avalanche energy was concentrated near the corner of the P-base region in the UIS mode. From this, the avalanche energy distribution differences of the four cell topologies were analyzed and compared. A theoretical model of avalanche heating per unit area is proposed, which shows that the avalanche energy density is inversely proportional to the proportion of avalanche energy concentration region. This study may contribute to the cell topology design of SiC MOSFETs under the application scenario with high avalanche reliability requirements.
...
To investigate the unclamped inductive switch (UIS) characteristics, 1200 V silicon carbide (SiC) planar MOSFETs with four cell topologies of linear, current sharing linear, square, and hexagon are designed and manufactured. The experimental platform was built and tested. The results show that the single pulse avalanche energy density of the linear cell topology is 1.69 times higher than that of the square and 1.49 times that of the hexagon. Further, the UIS process is simulated by using physical simulation, which shows that the avalanche energy was concentrated near the corner of the P-base region in the UIS mode. From this, the avalanche energy distribution differences of the four cell topologies were analyzed and compared. A theoretical model of avalanche heating per unit area is proposed, which shows that the avalanche energy density is inversely proportional to the proportion of avalanche energy concentration region. This study may contribute to the cell topology design of SiC MOSFETs under the application scenario with high avalanche reliability requirements.