The recording of biosignals, such as atrial electrograms (AEG), electrocardiograms (ECG), and electroencephalograms (EEG), is progressing towards the adoption of more dense electrode arrays in order to improve spatial and temporal resolution. The proliferation of channels necessitates some form of channel sharing technique so that efficient low power and area recording can be achieved.
In this thesis, a code-division multiplexed analog front-end is designed due to its efficient use of bandwidth in comparison to time and frequency multiplexing. Orthogonal coding schemes such as Walsh-Hadamard sequences are best suited for minimising cross-talk. These codes are typically implemented using an LUT or processor which becomes a significant overhead when a large number of channels are to be multiplexed. However, by investigating the sequences closely, a novel method of generating these codes from a clock signal using digital logic was devised. The proposed algorithm to generate these sequences on-chip provides significant area savings for sequences of length greater than 8, which makes the design scalable for a large number of channels,. The reduction in area ranges from a factor of 10 for a code length of 8 up to a factor as large as 200 for a code length of 128.
As orthogonal sequences require a low bandwidth, a low bandwidth low-noise amplifier and ADC were used for amplification and digitisation of the signal. By using digitally inspired analog blocks, such as an inverter-based amplifier, lower power consumption could be achieved.
The entire design was implemented to share 7 channels. The code generator, low-noise amplifier and ADC consume a total of 78.4μW, which corresponds to 11.2μW per channel. This is a 3.3x improvement to the design in [5] where pseudo-random sequences were used as the coding scheme. However, the design consumes more power than a state-of-the-art design reported in [6] which uses 1.97μW per channel. While the design is currently not optimized with respect to power consumption in comparison to the design in [6], the novel code generation technique reported in this thesis makes the design scalable for larger number of channels. This is because the area constraint of the LUT is no more the limiting factor in terms of area.

Brain-computer interfaces (BCIs) have the potential to revolutionize human-computer interaction and offer significant biomedical benefits by enabling applications such as closed-loop neuromodulation, mobility restoration for spinal cord injury patients, and therapies for neurodegenerative diseases. To fully leverage BCIs’ capabilities, it is crucial to enhance spatial resolution and robustness by increasing the number of recording channels and expanding brain area coverage. However, current approaches often focus on maximizing the channel count within a single recording analog front-end (AFE), limiting scalability and coverage.

This thesis introduces a novel architecture for a low-power and compact AFE, designed for seamless integration into a massively parallel array of distributed single-channel AFEs dedicated to micro-electrocorticography (μECoG) recording. The proposed AFE features a DC-coupled, chopper-stabilized low-noise boxcar sampler (LNB), followed by a passive switched-capacitor low-pass filter (SC-LPF) and a single-slope (SS) analog-to-digital converter (ADC). The LNB enhances anti-aliasing by introducing notches at multiples of the sampling frequency and effectively reduces chopping ripple. An 8-bit quantization is performed using a continuous time comparator synchronized with a globally distributed ramp across all channels of the array. The SS-ADC achieves a 12-bit resolution at the Nyquist rate (1 kSps) through oversampling at a rate of 16 times (OSR = 16).

Additionally, a novel electrode DC offset (EDO) cancellation loop prevents LNB saturation due to large EDO values, ensuring reliable performance in practical scenarios. Notably, this design eliminates the need for large AC coupling capacitors traditionally used for EDO cancellation, leading to a more compact design and improved scalability for high-density neural recording applications.

The proposed architecture is implemented at the transistor level in 40 nm CMOS technology and extensively validated through simulations. The AFE achieves exceptional area efficiency, with an estimated footprint of only 0.0028 mm² per channel. Moreover, the AFE achieves an input-referred noise (IRN) of 1.69 μV_rms over 0.5-500 Hz and provides an EDO compensation exceeding 100 mVpp. The design exhibits an input impedance of 71.4 MΩ and a common-mode rejection ratio (CMRR) of 80.94 dB. Additionally, the AFE achieves a signal-to-noise ratio (SNR) of 43.3 dB with a 1 mV_pp input signal. These results indicate that the presented AFE architecture, and specifically the novel compensation scheme, represent a promising approach for neural recording applications.

This thesis focuses on the design and optimization of Successive-approximation (SAR) Analog-to-Digital Converter (ADC), with a primary focus on enhancing the Bit Error Rate (BER). SAR ADCs are widely used in various applications due to their power-efficient characteristics. The critical point addressed in this research is improving the BER of synchronous SAR ADCs without the necessity to reduce the sampling speed...

Switched-capacitor power converters (SCPCs) have emerged as promising alternatives to traditional inductive power converters due to their CMOS integration capability and configurable conversion ratios. However, challenges such as output ripple, power efficiency, and transient response have hindered their widespread adoption. This article presents a novel Hybrid Hysteresis-CFM (HHC) control strategy that effectively addresses these issues.

The HHC strategy combines the best of both worlds, integrating hysteresis control and Continuous Frequency Modulation (CFM) control. During transient moments, the system utilizes a coarse/fine frequency tuning approach to rapidly reach the target frequency. Simultaneously, hysteresis control ensures that overshoot and undershoot are kept within predefined limits, significantly reducing output ripple during load transitions.

To enhance performance and versatility, the proposed system employs a Recursive Switched Capacitor (RSC) topology with adaptive capacitor sizing and 10-phase time-interleaving. This configuration enables configurable voltage-conversion ratios (VCRs) and high power conversion efficiency (PCE) across a wide input-output range.

Experimental results validate the effectiveness of the HHC SCPC. It demonstrates minimal overshoot and undershoot during load transition, maintains a low output voltage ripple during steady-state operation, and achieves high PCE. Comparative analysis with state-of-the-art DC-DC converters underscores the superior performance of the proposed system.

In summary, the Hybrid Hysteresis-CFM (HHC) control strategy offers a promising solution to enhance the capabilities of switched-capacitor power converters. Its ability to address output ripple, power efficiency, and transient response challenges makes it a valuable innovation for diverse applications requiring efficient power conversion.

Transmit digital-to-analog converters have become an essential building block for state-of-the-art Ethernet infrastructures. They are also one of the most significant sources of power consumption in an Ethernet physical layer (PHY) transceiver. These devices must maintain high linearity and a well-defined impedance of 100 Ω while operating at a speed of several GS/s. This thesis investigates the resistive digital-to-analog converter architecture, which is inherently more power-efficient than the widely used current-steering architecture. A technique to linearize the supply current, which reduces distortion caused by finite supply impedance, is proposed. The resulting 12-bit DAC designed in 180nm technology maintains INL and DNL error of +-0.6 LSB on a 12-bit level across temperature (-40 to 150°C) and corners. The DAC operates with a clock speed of 200 MS/s, achieving IM3 >85 dB at low frequency.

Residue amplification plays a key role in determining the energy efficiency, area and performance of high-speed pipelined ADCs. At its core, a residue amplifier simply consists of four transistors that transfer a differential input voltage to a capacitive load with the desired gain. However, in order to ensure gain accuracy over PVT, the core amplifier has to be augmented with extra circuitry to achieve high settling accuracy, at the expense of area and power dissipation. In this dissertation, techniques to improve the power efficiency of residue amplifiers were investigated, by adopting a two-pronged approach - 1. Developing new amplifier topologies which can achieve high resolution without relying on high DC-gain and settling accuracy, with the help of linearization in the analog domain, and 2. a deterministic calibration architecture which allows the calibration of linear gain error and distortion in background while achieving a fast convergence. @en

This thesis describes the design and implementation of power-efficient discrete-time amplifiers for data converter systems.@en

This brief presents a linearization technique for open-loop amplifiers. It utilizes the exponential {V}{-}{I} transfer of MOS transistors in weak-inversion together with a weak form of resistive degeneration. By using a specific relationship between the input transconductance and the source degeneration resistance, the amplifier is shown to have a significant reduction ( \sim 50\times ) in its third-order distortion component. Based on this linearization principle, two amplifier topologies are proposed by implementing the degeneration in (a) pseudo-differential and (b) common-mode configuration. The pseudo-differential degeneration scheme allows the amplifier to achieve more than 80dB linearity for 150mV {\text {pp-diff}} input swing at the expense of 35% lower power-efficiency. The common-mode degeneration eliminates this power penalty but exhibits 10dB worse linearity. To ensure an optimal linearity over process variation, a foreground calibration scheme is used to detect the nonlinearity. The nonlinearity correction is done by adjusting the bias current of the amplifier. The proof-of-concept amplifiers are constructed on a stripboard to demonstrate the effectiveness of the proposed linearization technique. With an input signal of 50mV {\rm pp{-}diff} , the two topologies achieve-105dB and-95dB HD3, respectively, improving the linearity of the state-of-The-Art open-loop amplifiers by at least 30dB.

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This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mV_pp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26 × compared with that of state-of-the-art high-linearity amplifiers.

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This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still maintaining sufficient linearity. This also allows the amplifier's gain to be corrected by adjusting its bias current. When combined with digital gain-error detection, in this case the split-ADC technique, the result is a power-efficient gain calibration scheme. In a prototype pipelined ADC, this scheme converges in only 12,000 clock cycles. With a near-Nyquist input, the ADC achieves 66-dB SNDR and 77.3-dB SFDR at 53 MS/s. Implemented in 40-nm CMOS, it dissipates 9 mW, of which 0.83 mW is consumed in the residue amplifiers. This represents a 1.8x improvement in power efficiency compared to state-of-the-art class-AB residue amplifiers.@en

A 12-bit pipelined analog-to-digital converter (ADC) using a new integration-based open-loop residue amplifier topology is presented. The amplifier distortion is cancelled with the help of an analog linearization technique based on a tunable input-driven active degeneration. Amplifier gain and nonlinearity errors are detected in background using split-ADC calibration technique. The mismatch between the two half-ADCs is minimized by sharing the residue amplifier between the two half-ADCs and adding the calibration offset over time. Based on this "split-over-time" calibration architecture, a two-lane prototype ADC was fabricated in 28-nm CMOS that achieves 64-dB signal-to-noise + distortion ratio and 77dB spurious-free dynamic range at Nyquist input after calibration. Operating at 280 MS/s, the ADC consumes 13 mW from 1-V supply, exhibiting a Schreier figure-of-merit of 164.3 dB. By dissipating only 0.4 mW in the residue amplifiers, the linearization technique helps the ADC achieve an improvement of at least 3 dB in Schreier FoM over existing state-of-the-art ADCs with comparable architectures.

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